<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: TwinDie Single Rank LPDDR4</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1186205#M165230</link>
    <description>&lt;P&gt;Hello Yurii&lt;/P&gt;&lt;P&gt;Right, it is BG0/1, typo. But the question is still up. In case I use TwinDie DDR memory I can use only one memory controller of iMX8MINI (MIMX8MM5DVTLZAA). To use two TwinDie chips/controllers I need two extra bits of the Bank Group (BG) signals to address other memory groups on the second memory chip?&lt;/P&gt;&lt;P&gt;Thanks, Ivan&lt;/P&gt;</description>
    <pubDate>Thu, 19 Nov 2020 19:01:45 GMT</pubDate>
    <dc:creator>IvanCa</dc:creator>
    <dc:date>2020-11-19T19:01:45Z</dc:date>
    <item>
      <title>TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1185333#M165133</link>
      <description>&lt;P&gt;Hello Everyone&lt;/P&gt;&lt;P&gt;Does i.MX.8M.Mini support TwinDie LPDDR4?&lt;/P&gt;&lt;P&gt;TwinDie requires additional DG1 for addressing x8 and ZQ.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="IvanCa_0-1605716936466.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/130393iCC2AFAB54CCD9D06/image-size/medium?v=v2&amp;amp;px=400" role="button" title="IvanCa_0-1605716936466.png" alt="IvanCa_0-1605716936466.png" /&gt;&lt;/span&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="IvanCa_1-1605716983154.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/130394i61BC8D421AE77DFC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="IvanCa_1-1605716983154.png" alt="IvanCa_1-1605716983154.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 18 Nov 2020 16:31:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1185333#M165133</guid>
      <dc:creator>IvanCa</dc:creator>
      <dc:date>2020-11-18T16:31:13Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1185784#M165177</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/180531"&gt;@IvanCa&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Looks like You mean signals BG0/1 for DDR4. Use Table 16 (DDR3L/LPDDR4/DDR4 connectivity)&lt;BR /&gt;of Hardware Development Guide for the i.MX8Mm:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/user-guide/IMX8MMHDG.pdf" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 19 Nov 2020 07:15:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1185784#M165177</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-11-19T07:15:45Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1186205#M165230</link>
      <description>&lt;P&gt;Hello Yurii&lt;/P&gt;&lt;P&gt;Right, it is BG0/1, typo. But the question is still up. In case I use TwinDie DDR memory I can use only one memory controller of iMX8MINI (MIMX8MM5DVTLZAA). To use two TwinDie chips/controllers I need two extra bits of the Bank Group (BG) signals to address other memory groups on the second memory chip?&lt;/P&gt;&lt;P&gt;Thanks, Ivan&lt;/P&gt;</description>
      <pubDate>Thu, 19 Nov 2020 19:01:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1186205#M165230</guid>
      <dc:creator>IvanCa</dc:creator>
      <dc:date>2020-11-19T19:01:45Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1187361#M165358</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/180531"&gt;@IvanCa&lt;/a&gt; &lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; Basically connection scheme for DDR4 is shown in the&amp;nbsp; Table 16 (DDR3L/LPDDR4/DDR4&lt;BR /&gt;connectivity). Signals BG0 and BG1 are shown there.&lt;BR /&gt;&amp;nbsp; But we&amp;nbsp; have not tested an example for the case with BG1 using.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Mon, 23 Nov 2020 09:09:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1187361#M165358</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-11-23T09:09:17Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1188836#M165484</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/180531"&gt;@IvanCa&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; Customers can use i.MX8Mn DDR4 design as an example.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/downloads/en/schematics/8MNANOD4-EVK-DF-SCH.7z" target="_blank"&gt;https://www.nxp.com/downloads/en/schematics/8MNANOD4-EVK-DF-SCH.7z&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Wed, 25 Nov 2020 09:42:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1188836#M165484</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-11-25T09:42:25Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189004#M165500</link>
      <description>&lt;P&gt;Hello Yurii.&lt;/P&gt;&lt;P&gt;Reference design schematic, you guess I can add one more DDR4 device since BG0 and BG1 are engaged?&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 25 Nov 2020 13:32:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189004#M165500</guid>
      <dc:creator>IvanCa</dc:creator>
      <dc:date>2020-11-25T13:32:29Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189018#M165503</link>
      <description>&lt;P&gt;It seems I got the idea already.&lt;/P&gt;&lt;P&gt;Thanks Yurii&lt;/P&gt;</description>
      <pubDate>Wed, 25 Nov 2020 13:58:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189018#M165503</guid>
      <dc:creator>IvanCa</dc:creator>
      <dc:date>2020-11-25T13:58:29Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189410#M165531</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/180531"&gt;@IvanCa&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;Yes - use&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;one more DDR4.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 26 Nov 2020 03:41:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1189410#M165531</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-11-26T03:41:21Z</dc:date>
    </item>
    <item>
      <title>Re: TwinDie Single Rank LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1191657#M165783</link>
      <description>&lt;P&gt;To be exact it is not related to the number of dies. Modern LPDDR4 use 4 or sometimes even 8 dies per component! Important for you is just that you correctly wire the address, bank, bank group and chip-select lines.&lt;/P&gt;&lt;P&gt;The largest LPDDR4 device currently on the market as 64Gbit (=8 GB!) and comes from Micron: &lt;A href="https://www.memorydistri.com/mt53e2g32d4dt-046%20wt:a.html" target="_blank"&gt;https://www.memorydistri.com/mt53e2g32d4dt-046%20wt:a.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Other manufacturers like Samsung, Hynix, Nanya go to maximum 32Gbit with their LPDDR4 and only offer the big 64Gb size on LPDDR4X (with lower I/O voltage of 0.6V) only. As I understand the i.MX8 processors are not able to operate LPDDR4X, but only LPDDR4.&lt;/P&gt;</description>
      <pubDate>Tue, 01 Dec 2020 14:05:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/TwinDie-Single-Rank-LPDDR4/m-p/1191657#M165783</guid>
      <dc:creator>twmemphis</dc:creator>
      <dc:date>2020-12-01T14:05:45Z</dc:date>
    </item>
  </channel>
</rss>

