https://community.nxp.com/t5/i-MX-Processors/iMX8M-LPDDR4-RPA/m-p/1185046#M165089 <P>I have two questions about the&nbsp;iMX8M RPA&nbsp; LPDDR4 calculation sheet.</P><P>1) In the&nbsp;DDRC_INIT7 register the&nbsp;LPDDR4 MR22: ODTE-CS field is set to '1'. If I'm correct than this means that the ODT is disabled for the CS signal in the LPDDR4 device.</P><P>What is the reason to only disable the ODT for the CS signals?</P><P>2) I discovered that the maximum row address setting for the iMX8M is 16. this means that a single rank memory configuration is limited to 8Gbit per channel. This limitation is not described in the documentation and in the RPA calculation sheet. can this be added?</P> Wed, 18 Nov 2020 08:25:01 GMT jeroenvanandel 2020-11-18T08:25:01Z https://community.nxp.com/t5/i-MX-Processors/iMX8M-LPDDR4-RPA/m-p/1185046#M165089 <P>I have two questions about the&nbsp;iMX8M RPA&nbsp; LPDDR4 calculation sheet.</P><P>1) In the&nbsp;DDRC_INIT7 register the&nbsp;LPDDR4 MR22: ODTE-CS field is set to '1'. If I'm correct than this means that the ODT is disabled for the CS signal in the LPDDR4 device.</P><P>What is the reason to only disable the ODT for the CS signals?</P><P>2) I discovered that the maximum row address setting for the iMX8M is 16. this means that a single rank memory configuration is limited to 8Gbit per channel. This limitation is not described in the documentation and in the RPA calculation sheet. can this be added?</P> Wed, 18 Nov 2020 08:25:01 GMT https://community.nxp.com/t5/i-MX-Processors/iMX8M-LPDDR4-RPA/m-p/1185046#M165089 jeroenvanandel 2020-11-18T08:25:01Z https://community.nxp.com/t5/i-MX-Processors/iMX8M-LPDDR4-RPA/m-p/1227874#M169128 <P>Recommend you to use the support value in the script.</P> Mon, 08 Feb 2021 10:15:05 GMT https://community.nxp.com/t5/i-MX-Processors/iMX8M-LPDDR4-RPA/m-p/1227874#M169128 Rita_Wang 2021-02-08T10:15:05Z