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    <title>topic Re: About SSI Receiver Timing with external clock. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1184287#M164991</link>
    <description>&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;I will inform this answer to my customer.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishi.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 17 Nov 2020 07:03:12 GMT</pubDate>
    <dc:creator>takayuki_ishii</dc:creator>
    <dc:date>2020-11-17T07:03:12Z</dc:date>
    <item>
      <title>About SSI Receiver Timing with external clock.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1182067#M164817</link>
      <description>&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a question about fall edge hold timing of FS in slave mode SSI.&lt;/P&gt;&lt;P&gt;In Figure 93. of datasheet IMX6DQPAEC rev3, Hold time of falling edge of AUDx_TXFS are defined&lt;/P&gt;&lt;P&gt;as more than 10ns from AUDx_RXC high to AUDx_TXFS low(SS30 and SS34 of Table 85).&lt;/P&gt;&lt;P&gt;In this time, AUDx_TXFS and AUDx_RXD of Master device are transition by rise edge of AUDx_RXC.&lt;/P&gt;&lt;P&gt;And Slave device will be latched each signals by falling edge of AUDx_RXC.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="SSI_MasterSlave.bmp" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/129779iB7231A3CCC984BD8/image-size/large?v=v2&amp;amp;px=999" role="button" title="SSI_MasterSlave.bmp" alt="SSI_MasterSlave.bmp" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;If so, SS30 and SS34 of Table85, It is difficult to keep 10ns as hold time because it is transition timing.&lt;/P&gt;&lt;P&gt;Is it correct to define SS30 and SS34 as "AUDx_RXC high to AUDx_TXFS&amp;nbsp; low"?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I think that it should be define as a transition timing like SS28 or SS32 or&lt;/P&gt;&lt;P&gt;a hold time of AUDx_TXFS, it must define from falling edge of AUDx_RXC like a SS41.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="SSI_HoldOrTransition.bmp" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/129785i086692DC51C3DFD3/image-size/large?v=v2&amp;amp;px=999" role="button" title="SSI_HoldOrTransition.bmp" alt="SSI_HoldOrTransition.bmp" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope I can hear from you soon.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;</description>
      <pubDate>Thu, 12 Nov 2020 07:06:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1182067#M164817</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2020-11-12T07:06:46Z</dc:date>
    </item>
    <item>
      <title>Re: About SSI Receiver Timing with external clock.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1182780#M164871</link>
      <description>&lt;P&gt;Hi Ishii&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;in Figure 93. of datasheet IMX6DQPAEC rev3, Hold time of falling edge of AUDx_TXFS are defined&lt;BR /&gt;&amp;gt;as more than 10ns from AUDx_RXC high to AUDx_TXFS low(SS30 and SS34 of Table 85)...&lt;BR /&gt;&amp;gt;.. think that it should be define as a transition timing like SS28 or SS32&lt;/P&gt;
&lt;P&gt;regarding your notes you are right, SS30 and SS34 timings should be depicted &lt;BR /&gt;as transition timing like SS28 or SS32.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Fri, 13 Nov 2020 04:09:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1182780#M164871</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-11-13T04:09:02Z</dc:date>
    </item>
    <item>
      <title>Re: About SSI Receiver Timing with external clock.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1183119#M164893</link>
      <description>&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your quick response.&lt;/P&gt;&lt;P&gt;Before update datasheet, is it ok to design SS30 and SS34 specification are not 10ns(min),&lt;/P&gt;&lt;P&gt;but same as SS28 and SS32(min=-10ns, max=15ns)?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 13 Nov 2020 11:49:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1183119#M164893</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2020-11-13T11:49:22Z</dc:date>
    </item>
    <item>
      <title>Re: About SSI Receiver Timing with external clock.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1183893#M164954</link>
      <description>&lt;P&gt;Hi Ishii&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I think yes.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Mon, 16 Nov 2020 14:04:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1183893#M164954</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-11-16T14:04:50Z</dc:date>
    </item>
    <item>
      <title>Re: About SSI Receiver Timing with external clock.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1184287#M164991</link>
      <description>&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;I will inform this answer to my customer.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ishi.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 17 Nov 2020 07:03:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-SSI-Receiver-Timing-with-external-clock/m-p/1184287#M164991</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2020-11-17T07:03:12Z</dc:date>
    </item>
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