imx6 sdma

2548903578 — Thu, 12 Nov 2020 03:14:41 GMT

I would like to ask what the <&sdma 3 7 1> parameters mean.

Re: imx6 sdma

ceggers — Thu, 12 Nov 2020 09:43:53 GMT

This parameter maps:

a SDMA event line (3)
a peripheral type (7)
a SDMA priority (1)

to a peripheral.

Each peripheral has one or two event lines internally connected to the SDMA controller. The SDMA controller has 48 event line inputs at all. In most (all?) i.MX6 reference manuals there is a chapter "3.3 SDMA event mapping" which shows the connection between peripherals and SDMA event lines.
Don't mistake SDMA event lines (48) with SDMA channels (32).

The possible peripheral types are listed in include/linux/platform_data/dma-imx.h:

enum sdma_peripheral_type {
    IMX_DMATYPE_SSI, /* MCU domain SSI */
    IMX_DMATYPE_SSI_SP, /* Shared SSI */
    IMX_DMATYPE_MMC, /* MMC */
    IMX_DMATYPE_SDHC, /* SDHC */
    IMX_DMATYPE_UART, /* MCU domain UART */
    IMX_DMATYPE_UART_SP, /* Shared UART */
    IMX_DMATYPE_FIRI, /* FIRI */
    IMX_DMATYPE_CSPI, /* MCU domain CSPI */
    IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
...
}
So peripheral type 7 is IMX_DMATYPE_CSPI which means SPI over AHB bus.

The SDMA priorities are reverse mapped to reverse mapped to hardware priorities of the SDMA CPU (also include/linux/platform_data/dma-imx.h):

enum imx_dma_prio {
    DMA_PRIO_HIGH = 0, /* highest possible prio --> hardware prio 3 of 7 */
    DMA_PRIO_MEDIUM = 1, /* medium prio --> hardware prio 2 of 7 */
    DMA_PRIO_LOW = 2   /* lowest prio -> hardware prio 1 of 7 */
};

I would highly appreciate if NXP could provide patches for using preprocessor defines instead of magic numbers in the device tree files. Device tree support preprocessor, but no C style enums.

If you have more questions regarding the SDMA, you can also contact me directly (there is a function in the forum for private messages). I don't scan the forum for new posts everyday...

regards
Christian

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imx6 sdma

Re: imx6 sdma