About tzasc on imx6q sabre sd borad: How to trigger the synchronous external data abort

xushouyin17 — Tue, 10 Nov 2020 01:53:47 GMT

The current experimental development board is IMx6Qsabresd, the environment is IMx Uboot 4.14 + IMX Linux 4.14 + IMx optee OS, 4M region is set as the normal world read-only, the secure world can read and write
Expectations:
Synchronous External Data ABORT is triggered into Monitor mode when the normal world writes to this region
I have done :
The cache has been set to write through, the SCR.EA bit has been set to 1, IOMUX GPR9, and CCM GPR3 has been set

In the normal world, I write the value to this region, then read it, the value is incorrect. It means that the tzasc is worked
Does anyone know how to trigger this exception?

Re: About tzasc on imx6q sabre sd borad: How to trigger the synchronous external data abort

nxf63969 — Wed, 18 Nov 2020 21:19:17 GMT

Hi shouyin xu,

I quote the ARM Cortex-A9 TRM: "External aborts can be configured to trap to Monitor mode by setting the EA bit in the SCR".

I think the External abort registers that are mainly involved are SCR and DFSR/IFSR so it is already active.

The DFSR register gives you additional details on the abort to know the Fault Type and the cause (Read/Write).

Check that status register when you try to write to that memory region.

Regards,

Luis.

topic About tzasc on imx6q sabre sd borad: How to trigger the synchronous external data abort in i.MX Processors

About tzasc on imx6q sabre sd borad: How to trigger the synchronous external data abort

Re: About tzasc on imx6q sabre sd borad: How to trigger the synchronous external data abort