topic Re: PLL4 (audio PLL) on CLKO2 in i.MX Processors

PLL4 (audio PLL) on CLKO2

johannesdev — Tue, 20 Oct 2020 14:26:12 GMT

Hi!

For an external chip I would need a 27MHz clock signal which I'd like to create using PLL4 within the I.MX6UL. Currently I'm in an evaluation stage so I'm using the devmem command within busybox to write and read registers.

So far I started successfully PLL4 with the appropriate registers. At least PLL4's lock-bit can be read as locked, as the MSB of the 32 bits is high:

# devmem 0x20C8070 32 0x8000201F

Next step would be to output the clock on pin A2, CCM_CLKO2. However, I cannot achieve this using the CCM_CCOSR register. I try the following here:

CLKO_SEL = 1111 to get the PLL4 output clk
CLKO1_EN = 1 for enabling the output pin
and
CLK_OUT_SEL = 1 for outputting CLKO1 on CLKO2

Since I used the CLK_OUT_SEL bit, CLKO2 should now show any transition (at least any vital sign of the PLL). However, I does not :-(. This stays the same when I try any other CLKO1 clock inputs. Thus, what is the right setting of CCM_CCOSR? Should be CLKO2_EN = 0 and CLKO2_SEL[..] = XXX as another post shows ?

One more thought: When I output mmdc_clk on CLKO2 (via CCM_CLKO2 and /8 using the corresponding divider), I see a 50MHz signal on the pin. Hence the IOMUX setting is correct.

Re: PLL4 (audio PLL) on CLKO2

igorpadykov — Wed, 21 Oct 2020 04:02:07 GMT

Hi johannesdev

>..CLKO2 should now show any transition (at least any vital sign of the PLL)

one can try to test it on i.MX6UL EVK board (mux JTAG_TDO pad) with Demo Images

from https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX?tab=In-Depth_Tab

Use default PLL4 settings, for setting of CCM_CCOSR use memtool

https://source.codeaurora.org/external/imx/imx-test/tree/test/memtool?h=imx_5.4.24_2.1.0

Note PLL4 can not be programmed directly to 27MHz as allowable range is 650 MHz ~1.3 GHz

according to sect.4.4 PLL’s electrical characteristics

i.MX 6UltraLite Applications Processors for Consumer Products Data Sheet

Best regards
igor

Re: PLL4 (audio PLL) on CLKO2

johannesdev — Wed, 21 Oct 2020 11:16:14 GMT

Hi igor,

thank you for your reply. I totally forgot that CLKO1 can be output on JTAG_TMS as well. Here I can easily output the 27MHz clock (whereas the PLL4 output is approx. 860MHz). Although the CLK_OUT_SEL bit stays a mystery to me.

Best regards,
johannes