topic Re: DDR3 data inverted in i.MX Processors

DDR3 data inverted

hailiu — Mon, 19 Oct 2020 07:36:20 GMT

I am debugging DDR3 (micron M$41k512M16HT using dummy register write and read. When I write a number 0xFFFFFFFF, i got the number 0x00000000 in all the 8 dummy read registers. When I write a number 0x00550055, I get the number 0xAAAAAAAA,0xFFFFFFFF,0xAAAAAAAA,0xFFFFFFFF,0xAAAAAAAA,0xFFFFFFFF,0xAAAAAAAA,0xFFFFFFFF.

when I write a number 0xAAAAAAAA, i get the number 0x55555555 in all 8 dummy register. When I write a number 0xAB5DC432, I got the number 0xCDCDCDCD, 0x3B3B3B3B, 0xA2A2A2A2,0x54545454. It seems that erery dummy register hold one byte inverted of the write value. The ZQCL and write level calibration can be passed. somethings wrong with my settings?

I saw a line in the reference manual in the DQS gating calibration section :

atep 9: MMDC reset the read FIFO (to the inverted pre-defined/MPR value), what does this mean?

below is a piece of my test code:

CMD=(0x02<<4); //one refresh command send to DDR
HW_MMDC_MDSCR_WR(MMDC1_BASE,CON_REQ|CMD_CS|CMD); //DDR refresh
while(!((HW_MMDC_MDSCR_RD(MMDC1_BASE))&0x00004000))
{

}

CMD=(0x05<<4);
HW_MMDC_MDSCR_WR(MMDC1_BASE,CON_REQ|CMD|CMD_CS); //pre-charge all banks
while(!((HW_MMDC_MDSCR_RD(MMDC1_BASE))&0x00004000))
{

}
PDV2=(0xAC5D<<16);
PDV1=0xC432;
HW_MMDC_MPPDCMPR1_WR(MMDC1_BASE, PDV1|PDV2); //set pre-defined value which will be written to DDR device
SW_DUMMY_WR=1;
HW_MMDC_MPSWDAR0_WR(MMDC1_BASE,SW_DUMMY_WR); //write predefined value to DDR bank 0, row 0 col 0
while ((HW_MMDC_MPSWDAR0_RD(MMDC1_BASE)&0x00000001))
{

}
RST_RD_FIFO=(0x1<<31);
HW_MMDC_MPDGCTRL0_WR(MMDC1_BASE,RST_RD_FIFO);
while((HW_MMDC_MPDGCTRL0_RD(MMDC1_BASE)&0x80000000))
{

} //wait fifo reset
HW_MMDC_MPDGCTRL0_WR(MMDC1_BASE,RST_RD_FIFO); //reset rd fifo second times
while((HW_MMDC_MPDGCTRL0_RD(MMDC1_BASE)&0x80000000))
{

} //wait fifo reset

HW_MMDC_MPSWDAR0_WR(MMDC1_BASE,0x02); //read value from to DDR bank 0, row 0 col 0
while ((HW_MMDC_MPSWDAR0_RD(MMDC1_BASE)&0x00000002))
{

}
readValue8=HW_MMDC_MPSWDAR0_RD(MMDC1_BASE);
readValue=HW_MMDC_MPSWDRDR0_RD(MMDC1_BASE);
readValue1=HW_MMDC_MPSWDRDR1_RD(MMDC1_BASE);
readValue2=HW_MMDC_MPSWDRDR2_RD(MMDC1_BASE);
readValue3=HW_MMDC_MPSWDRDR3_RD(MMDC1_BASE);

Re: DDR3 data inverted

igorpadykov — Mon, 19 Oct 2020 08:53:17 GMT

Hi hailiu

what processor (full part number) used in the case. For i.MX6 series one can look at

below link, ddr test package has some sample scripts

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6-7-DDR-Stress-Test-Tool/ta-p/1108221

Best regards
igor

Re: DDR3 data inverted

hailiu — Tue, 20 Oct 2020 00:26:59 GMT

thank you very much. I checked the reference manual again carefully, found that PDV2 and PDV1 is inverted. I guess that's is why I get an inverted value.

Re: DDR3 data inverted

hailiu — Tue, 20 Oct 2020 00:54:16 GMT

I use MCIMX6S5DVM10AD.

Re: DDR3 data inverted

hailiu — Tue, 20 Oct 2020 02:11:42 GMT

dear igorpadykov,

If i write the value 0xAACC3553 to DDR3 bank 0 row 0 col 0 using dummy software write (with register MPSWDAR0), what values should I get in the dummy read register0-7 when I doing a dummy software read(with register MPSWDAR0)?

thank you very much.

Re: DDR3 data inverted

igorpadykov — Tue, 20 Oct 2020 04:32:46 GMT

I do not think that it is feasible to perform such "dummy" write/reads.

For simple ddr test one can refer to SDK example (ddr_test.c in 1.1.0_iMX6_Platform_SDK.zip)

available on

https://community.nxp.com/t5/i-MX-Processors/SMP-Enable-in-IMX6/m-p/542111

Best regards
igor

Re: DDR3 data inverted

hailiu — Tue, 20 Oct 2020 06:12:13 GMT

thank you very much. I am going to see these documents.