<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: iMX8MM ECSPI DMA Issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1167623#M163478</link>
    <description>&lt;P&gt;Hi NXP Team,&lt;/P&gt;&lt;P&gt;Any possible solution or suggestion to me regarding the above query.&lt;/P&gt;&lt;P&gt;Thank you, Sreedhar&lt;/P&gt;</description>
    <pubDate>Wed, 14 Oct 2020 18:00:12 GMT</pubDate>
    <dc:creator>sreedhar_appala</dc:creator>
    <dc:date>2020-10-14T18:00:12Z</dc:date>
    <item>
      <title>iMX8MM ECSPI DMA Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1166322#M163345</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am working with i.MX8MM EVK and 4.19.35.1.1.0 Yocto distribution.&lt;/P&gt;&lt;P&gt;We have interfaced a slave to ECSPI2 pins exposed on J1003 of i.MX8MM EVK.&lt;/P&gt;&lt;P&gt;ECSPI2 is configured as Master, CPOL = CPHA = 0,&amp;nbsp;Bits Per Word&amp;nbsp; = 8&lt;/P&gt;&lt;P&gt;If&amp;nbsp; SPI burst &amp;lt; 32 bytes PIO mode transfer&lt;/P&gt;&lt;P&gt;If&amp;nbsp;&amp;nbsp;SPI burst &amp;gt;= 32 bytes DMA mode transfer is programmed in spi-imx.c platform driver.&lt;/P&gt;&lt;P&gt;PIO mode works well for SPI burst of 8,16 and 24 bytes (multiple of 8 bytes)&lt;/P&gt;&lt;P&gt;But when we try to use DMA transfer for SPI burst size of 32 / 64 bytes, SPI transfer fails.&lt;/P&gt;&lt;P&gt;After looking at the platform driver code spi-imx.c, I think some piece of code / patch is missing for DMA transfer to work.&lt;/P&gt;&lt;P&gt;Could you please let me know your comments and possible direction for solving this issue.&lt;/P&gt;&lt;P&gt;Thank you, Sreedhar&lt;/P&gt;</description>
      <pubDate>Mon, 12 Oct 2020 21:29:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1166322#M163345</guid>
      <dc:creator>sreedhar_appala</dc:creator>
      <dc:date>2020-10-12T21:29:33Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8MM ECSPI DMA Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1167623#M163478</link>
      <description>&lt;P&gt;Hi NXP Team,&lt;/P&gt;&lt;P&gt;Any possible solution or suggestion to me regarding the above query.&lt;/P&gt;&lt;P&gt;Thank you, Sreedhar&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2020 18:00:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1167623#M163478</guid>
      <dc:creator>sreedhar_appala</dc:creator>
      <dc:date>2020-10-14T18:00:12Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8MM ECSPI DMA Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1169897#M163691</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Could you try with latest release and check if the same behavior is seen?&lt;BR /&gt;whether L5.4.24_2.1.0 or L5.4.47_2.2.0&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Tue, 20 Oct 2020 00:42:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MM-ECSPI-DMA-Issue/m-p/1169897#M163691</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2020-10-20T00:42:44Z</dc:date>
    </item>
  </channel>
</rss>

