PWM Missing interrupts on 5121 GPT peripherical

juanba — Fri, 09 Oct 2020 20:48:47 GMT

I am trying to operate a custom Linux driver for the MCP5121 GPT peripherical unit working as a PWM. The driver settles an interrupt service with the intention to reload a new duty cycle with every hit.

I have checked that the GPT interrupt vector is properly installed and serviced using the IPIC force interrupt register SIFCR(0x50).

I run a relatively old Linux kernel and the pwm device driver model is not available. So, the pwm software usability interface is assembled with write system calls. A parameter of 32 bits encodes the window time, the period and the duty cycle/1000.

With below testing values, the driver settles the involved registers as the following, we run with the IPS clocking to 66Mhz(15ns):

# echo 0xff0fffff >/dev/mpc5121-pwm
mpc5121-pwm( pwm_open)
mpc5121-pwm( pwm_write)
Mode (0x010) : 0x00000103( 0b0000000100000011 )
pwm.command 0xff0fffff vs 0xff0fffff : Scheduling(4)
Single Shot of 6200(msec) 65104(Hz) duty 783/1000, 15 nsec/tick
PWMOffset (0x018) : duty/1000 783 encoded as 0x03210000: 12015(nsec)
Counter (0x014) : Freq 65104(Hz) encoded as 0x00010400: 15360(nsec)

The Mode(0x010) GPT register valued like this, should enable the interrupt generation with the bit INTEN toggled and the TIMER_MS field valued as PWM(0x03) operation valued

After some ticks on the the Linux shell through the read driver call I see the following:

# cat /dev/mpc5121-pwm
mpc5121-pwm( pwm_open)
mpc5121-pwm( pwm_read)
Deadline of 6200 msec vs measurement of 0 -> missed (overrun 0)
Mode (0x010) : 0x00000103( 0b0000000100000011 )
Counter (0x014) : 0x00010400
PWM (0x018) : 0x03210000
Status (0x01c) : 0x00006004

IPIC
SIPNR_H (0x008) : 0x00000000
SIMSR_H (0x020) : 0x008011f9
SIPRR_D (0x1ca) : 0x00000000

# cat /dev/mpc5121-pwm
mpc5121-pwm( pwm_open)
mpc5121-pwm( pwm_read)
Deadline of 6200 msec vs measurement of 0 -> missed (overrun 0)
Mode (0x010) : 0x00000103( 0b0000000100000011 )
Counter (0x014) : 0x00010400
PWM (0x018) : 0x03210000
Status (0x01c) : 0x00002004

IPIC
SIPNR_H (0x008) : 0x00000000
SIMSR_H (0x020) : 0x008011f9
SIPRR_D (0x1ca) : 0x00000000

# cat /dev/mpc5121-pwm
mpc5121-pwm( pwm_open)
mpc5121-pwm( pwm_read)
Deadline of 6200 msec vs measurement of 0 -> missed (overrun 0)
Mode (0x010) : 0x00000103( 0b0000000100000011 )
Counter (0x014) : 0x00010400
PWM (0x018) : 0x03210000
Status (0x01c) : 0x00001004

IPIC
SIPNR_H (0x008) : 0x00000000
SIMSR_H (0x020) : 0x008011f9
SIPRR_D (0x1ca) : 0x00000000

The registers value seem stable on the PWM specifications and the timer operative. However, the weird thing is that the GPT unit is not interrupting the CPU and obviously the ISR is not threaded under the PWM behaviour.

I have checked as well the interrupt flow using the pure Timer operation with not IO hardware involved TIMER_MS(0b1xx). The PWM modality seems on going, the overflow fields on the Status(0x01c) are moving over its dynamic range of 0 to 7 (3bits).

Should I check other SOC parts? Where can I view some real example code about this particular operation mode?

Re: PWM Missing interrupts on 5121 GPT peripherical

Pavel — Tue, 13 Oct 2020 02:53:49 GMT

See the Section 17.1.1.3 of the MPC5121 Reference Manual:

In PWM mode, the I/O pin is an Output. The user can program period and width values to create an adjustable, repeating output waveform on the I/O pin. A CPU interrupt can be generated at the beginning of each PWM Period, at which time a new Width value can be loaded. The new Width value, which represents ON time, is automatically applied at the beginning of the next period. There is no interrupt at the beginning of the first PWM Period. This mode is suitable for PWM audio encoding.

Attached file contains simple GPT examples. PWM example does not use interrupts, and the second example is example for interrupt using.

Re: PWM Missing interrupts on 5121 GPT peripherical

juanba — Wed, 14 Oct 2020 16:18:52 GMT

As far as i understand.

My post is related with that i am fully unable to trigger this feature: A CPU interrupt can be generated at the beginning of each PWM Period

This interrupt is a MUST to reload the new duty value on the carrier if the PWM is a wave generator case of use.

The example labeled as GPT_IRQ.zip use the timer under mode 0b100 which is a "typical" timer where the full IO activity is software driven aka on the ISR time which is exactly what we would like to avoid. The idea behind this usual stuff is that the software has one cycle off period out of pressure, so the real time behaviour is extended one period at least.

Thanks for your support..

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PWM Missing interrupts on 5121 GPT peripherical

Re: PWM Missing interrupts on 5121 GPT peripherical

Re: PWM Missing interrupts on 5121 GPT peripherical