i.MX ProcessorsのトピックRe: MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

Issac_20200908 — Wed, 14 Oct 2020 04:34:51 GMT

Hardware setup:

(1)ONLY ONE Camera (parallel image sensor output to DS90UB933,1080p,25fps,YUV422)

(2)Deserializer is DS90UB960(x4 lane), and is connected to MIPI CSI-2 interface of IMX6Q processor.

Theoretically, MIPI data rate of IMX6Q for 1080p,25fps,YUV422 will be 279.933Mbps per lane.

Questions:

(1)In our case,DS90UB960 is set to 400Mbps for i.MX6Q in x4 lanes mode.

What value we should use for MIPI_CSI2_PHY_TST_CTRL1 resister? 400MHz or 279.933MHz

(2)When DS90UB960 is set to 400Mbps per lane, video is correct only when MIPI_CSI2_PHY_TST_CTRL1 is set to 0x0E (value for 500~550Mhz frequency range and 549Mhz exact value). WHY?

(3)We wanna to run DS90UB960 to 800Mbps x4 Lanes. When DS90UB960 is set to 800Mbps per lane, no valid value for MIPI_CSI2_PHY_TST_CTRL1 to show a correct image. We get a rolling image with several angular stripes. Any suggestion for us to debug it?

Re: MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

igorpadykov — Wed, 14 Oct 2020 07:48:11 GMT

Hi Issac_20200908

for setting frequency details one can look at below link:

"For example, if the clock lane frequency is 128MHz, the clock range should

be 250-270MHz because of DDR clock mode.."

https://community.nxp.com/t5/i-MX-Processors/Some-Experience-When-Enable-MIPI-Camera/m-p/228959#328301

For debugging try unit test, mxc_v4l2_tvin.out, some examples can be found on

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX6DQ-MAX9286-MIPI-CSI2-720P-camera-surround-view-solution-for/ta-p/1116501

https://source.codeaurora.org/external/imx/imx-test/tree/test/mxc_v4l2_test?h=imx_5.4.24_2.1.0

Best regards
igor

Re: MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

Issac_20200908 — Wed, 14 Oct 2020 10:45:49 GMT

Thank you,igor.

in all docs referred above, IMX6Q's MIPI DPHY is said to match sensor clock and MIPI_CSI2_PHY_TST_CTRL1 are calculated based on video image data rate.

In our case,DS90UB960 works as a camera sensor. However, DS90UB960 can only use 400Mbps or 800Mbps per lane when interfacing to IMX6Q, and far large than video image data rate(279.933Mbps per lane).

Does MIPI_CSI2_PHY_TST_CTRL1 should use value 0x28(300Mbps) no matter DS90UB960 DPHY's actual data rate is 400Mbps or 800Mbps?

Re: MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

igorpadykov — Wed, 14 Oct 2020 14:46:31 GMT

Hi Issac_20200908

if DS90UB960 works as a camera sensor and use 400Mbps per lane then
(as said in above example) "clock range should be 800MHz because of DDR clock mode.."

Best regards
igor

Re: MIPI_CSI2_PHY_TST_CTRL1 setting when interfacing DS90UB960 to IMX6Q

Issac_20200908 — Thu, 15 Oct 2020 04:21:47 GMT

Thanks, igor.

MIPI_CSI2_PHY_TST_CTRL1 value is based on MIPI transimitter's DPHY clock frequency as you said.

We have tested OK for 400Mbps x4 lane and 800Mbps x3 Lane with DS90UB960.