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    <title>topic Re: iMX8M mini DDR4 data bits swap in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1167003#M163425</link>
    <description>&lt;P&gt;Thank you for the reply.&lt;/P&gt;&lt;P&gt;Good to know that there are no limitations on swapping the DDR4 data lines, however how do we tell the DDR4 tool &lt;EM&gt;&lt;STRONG&gt;MX8M_Mini_DDR4_RPA_v1&lt;/STRONG&gt;&lt;STRONG&gt;1&lt;/STRONG&gt;&lt;/EM&gt; to do the DQ lanes swapping in order to start a DDR4 stress test for our custom design?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;attached is the MX8M_Mini_DDR4_RPA_v11 file we use.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thank you!&lt;/P&gt;</description>
    <pubDate>Wed, 14 Oct 2020 00:34:36 GMT</pubDate>
    <dc:creator>saidjazouly</dc:creator>
    <dc:date>2020-10-14T00:34:36Z</dc:date>
    <item>
      <title>iMX8M mini DDR4 data bits swap</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1166792#M163409</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;we have a custom design based on i.MX8 with a DDR4 memory.&lt;/P&gt;&lt;P&gt;we customized the design so that the i.MX8M DDR4 data lines are swapped and not routed directly to the DDR4 in the same order of pins, for ex:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="saidjazouly_0-1602598697990.png" style="width: 658px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/127335iF03ECB89DFEBE673/image-dimensions/658x370?v=v2" width="658" height="370" role="button" title="saidjazouly_0-1602598697990.png" alt="saidjazouly_0-1602598697990.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In a previous design where we used LPDDR4 memory, we had a special tab in the excel tool MX8M_Mini_LPDDR4_RPA_v15 to make the bit swapping:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="saidjazouly_1-1602598776725.png" style="width: 663px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/127336i9D8FEF604F6BB5D8/image-dimensions/663x325?v=v2" width="663" height="325" role="button" title="saidjazouly_1-1602598776725.png" alt="saidjazouly_1-1602598776725.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However we don't have such a tab in the DDR4 tool MX8M_Mini_DDR4_RPA_v11&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;How can we perform the data bit swapping in this case?&lt;/LI&gt;&lt;LI&gt;Is it possible to do a complete DDR4 configuration and perform the stress tests and get the timings using "Config Tools for i.MX v7"&lt;/LI&gt;&lt;LI&gt;Any helpful procedure that we can follow?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Thanks very much.&lt;/P&gt;</description>
      <pubDate>Tue, 13 Oct 2020 14:24:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1166792#M163409</guid>
      <dc:creator>saidjazouly</dc:creator>
      <dc:date>2020-10-13T14:24:15Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8M mini DDR4 data bits swap</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1167002#M163424</link>
      <description>&lt;P&gt;Hi saidjazouly ,&lt;/P&gt;
&lt;P&gt;For iMX8MM-EVK, we have 2 versions, one is i.mx8mm + lpddr4, the other is imx8mm+DDR4. attachment is 8MMINID4-EVK-DESIGNFILES. you can refer to it to design your product.&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN class="" title=""&gt;For DDR4, there is no restriction on the exchange of data bits, as you can see in this design files.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN class="" title=""&gt;Have a nice day!&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN class="" title=""&gt;B.R,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN class="" title=""&gt;weidong&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2020 00:26:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1167002#M163424</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2020-10-14T00:26:39Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8M mini DDR4 data bits swap</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1167003#M163425</link>
      <description>&lt;P&gt;Thank you for the reply.&lt;/P&gt;&lt;P&gt;Good to know that there are no limitations on swapping the DDR4 data lines, however how do we tell the DDR4 tool &lt;EM&gt;&lt;STRONG&gt;MX8M_Mini_DDR4_RPA_v1&lt;/STRONG&gt;&lt;STRONG&gt;1&lt;/STRONG&gt;&lt;/EM&gt; to do the DQ lanes swapping in order to start a DDR4 stress test for our custom design?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;attached is the MX8M_Mini_DDR4_RPA_v11 file we use.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thank you!&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2020 00:34:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-mini-DDR4-data-bits-swap/m-p/1167003#M163425</guid>
      <dc:creator>saidjazouly</dc:creator>
      <dc:date>2020-10-14T00:34:36Z</dc:date>
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