https://community.nxp.com/t5/i-MX-Processors/iMX7Solo-Dual-DDR-bit-swapping/m-p/1163926#M163046 <P>Hello.</P><P>I'm designing the board with iMX7S processor. I'm using LPDDR2 memory for this application.</P><P>Is it possible to swap bits inside the data lanes for simplifying PCB layout? (I didn't find any mention on it in application notes or datasheet).</P><P><SPAN>I would be grateful for your prompt reply.</SPAN></P><P><SPAN>Igor.</SPAN></P> Wed, 07 Oct 2020 13:10:23 GMT igal_kagan 2020-10-07T13:10:23Z https://community.nxp.com/t5/i-MX-Processors/iMX7Solo-Dual-DDR-bit-swapping/m-p/1163926#M163046 <P>Hello.</P><P>I'm designing the board with iMX7S processor. I'm using LPDDR2 memory for this application.</P><P>Is it possible to swap bits inside the data lanes for simplifying PCB layout? (I didn't find any mention on it in application notes or datasheet).</P><P><SPAN>I would be grateful for your prompt reply.</SPAN></P><P><SPAN>Igor.</SPAN></P> Wed, 07 Oct 2020 13:10:23 GMT https://community.nxp.com/t5/i-MX-Processors/iMX7Solo-Dual-DDR-bit-swapping/m-p/1163926#M163046 igal_kagan 2020-10-07T13:10:23Z https://community.nxp.com/t5/i-MX-Processors/iMX7Solo-Dual-DDR-bit-swapping/m-p/1164228#M163072 <P>Hi Igor</P> <P>&nbsp;</P> <P>this is general question, for example answer can be found on</P> <P><A href="https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Zynq-LPDDR2-DQ-Swap-Question/td-p/396867" target="_blank">https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Zynq-LPDDR2-DQ-Swap-Question/td-p/396867</A></P> <P>&nbsp;</P> <P>Best regards<BR />igor</P> Thu, 08 Oct 2020 00:39:17 GMT https://community.nxp.com/t5/i-MX-Processors/iMX7Solo-Dual-DDR-bit-swapping/m-p/1164228#M163072 igorpadykov 2020-10-08T00:39:17Z