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    <title>topic Re: LPDDR4 issue in DDR Stress Tool in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163208#M162950</link>
    <description>&lt;P&gt;Thanks Igor for your quick response.&lt;/P&gt;&lt;P&gt;We will verify the checks suggested by you.&lt;/P&gt;</description>
    <pubDate>Tue, 06 Oct 2020 04:50:32 GMT</pubDate>
    <dc:creator>sahilnayak</dc:creator>
    <dc:date>2020-10-06T04:50:32Z</dc:date>
    <item>
      <title>LPDDR4 issue in DDR Stress Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1162804#M162895</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are running our script file for 4GB LPDDR4 in the mscale DDR Stress tool and below are the logs of it. We are getting Invalid Target print after all configurations are done for LPDDR4:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_train1d_string.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_train2d_string.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_pmu_train_1d_imem.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_pmu_train_1d_dmem.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_pmu_train_2d_imem.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading file 'bin\lpddr4_pmu_train_2d_dmem.bin' ..Done&lt;/P&gt;&lt;P&gt;Downloading IVT header...Done&lt;BR /&gt;Downloading file 'bin\m850_ddr_stress_test.bin' ...Done&lt;/P&gt;&lt;P&gt;Download is complete&lt;BR /&gt;Waiting for the target board boot...&lt;/P&gt;&lt;P&gt;********Found PMIC PF0100**********&lt;/P&gt;&lt;P&gt;*************************************************************************&lt;/P&gt;&lt;P&gt;*************************************************************************&lt;/P&gt;&lt;P&gt;*************************************************************************&lt;BR /&gt;MX8 DDR Stress Test V3.10&lt;BR /&gt;Built on Feb 5 2020 14:08:44&lt;BR /&gt;*************************************************************************&lt;/P&gt;&lt;P&gt;--Set up the MMU and enable I and D cache--&lt;BR /&gt;- This is the Cortex-A53 core&lt;BR /&gt;- Check if I cache is enabled&lt;BR /&gt;- Enabling I cache since it was disabled&lt;BR /&gt;- Push base address of TTB to TTBR0_EL3&lt;BR /&gt;- Config TCR_EL3&lt;BR /&gt;- Config MAIR_EL3&lt;BR /&gt;- Enable MMU&lt;BR /&gt;- Data Cache has been enabled&lt;BR /&gt;- Check system memory register, only for debug&lt;/P&gt;&lt;P&gt;- VMCR Check:&lt;BR /&gt;- ttbr0_el3: 0x91d000&lt;BR /&gt;- tcr_el3: 0x2051c&lt;BR /&gt;- mair_el3: 0x774400&lt;BR /&gt;- sctlr_el3: 0xc01815&lt;BR /&gt;- id_aa64mmfr0_el1: 0x1122&lt;/P&gt;&lt;P&gt;- MMU and cache setup complete&lt;/P&gt;&lt;P&gt;*************************************************************************&lt;BR /&gt;ARM clock(CA53) rate: 800MHz&lt;BR /&gt;DDR Clock: 1600MHz&lt;/P&gt;&lt;P&gt;============================================&lt;BR /&gt;DDR configuration&lt;BR /&gt;DDR type is LPDDR4&lt;BR /&gt;Data width: 32, bank num: 8&lt;BR /&gt;Row size: 16, col size: 10&lt;BR /&gt;Two chip selects are used&lt;BR /&gt;Number of DDR controllers used on the SoC: 1&lt;BR /&gt;Density per chip select: 2048MB&lt;BR /&gt;Density per controller is: 4096MB&lt;BR /&gt;Total density detected on the board is: 4096MB&lt;BR /&gt;============================================&lt;/P&gt;&lt;P&gt;Invalid Target(Request=0xd, CoreID=0xd03)&lt;/P&gt;&lt;P&gt;*************************************************************************&lt;/P&gt;&lt;P&gt;We are getting proper voltage on LPDDR4 rails and power sequence is also proper.&lt;/P&gt;&lt;P&gt;Please help us to identify that why are we getting Invalid Target and how we can resolve it.&lt;/P&gt;</description>
      <pubDate>Mon, 05 Oct 2020 08:31:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1162804#M162895</guid>
      <dc:creator>sahilnayak</dc:creator>
      <dc:date>2020-10-05T08:31:27Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 issue in DDR Stress Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163159#M162935</link>
      <description>&lt;P&gt;Hi sahilnayak&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;for "Invalid Target" error one can check if correct part number was&lt;/P&gt;
&lt;P&gt;selected in field "Target" of ddr test. Also it may be caused by hardware,&lt;/P&gt;
&lt;P&gt;may be suggested to check processor voltages, use datasheet and hardware guide&lt;/P&gt;
&lt;P&gt;for reference :&lt;/P&gt;
&lt;P&gt;&lt;A id="relatedDocsClick_1" href="https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products&lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A id="relatedDocsClick_5" href="https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQHDG" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX8M Hardware Developer’s Guide&lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Tue, 06 Oct 2020 00:25:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163159#M162935</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-10-06T00:25:55Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 issue in DDR Stress Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163208#M162950</link>
      <description>&lt;P&gt;Thanks Igor for your quick response.&lt;/P&gt;&lt;P&gt;We will verify the checks suggested by you.&lt;/P&gt;</description>
      <pubDate>Tue, 06 Oct 2020 04:50:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163208#M162950</guid>
      <dc:creator>sahilnayak</dc:creator>
      <dc:date>2020-10-06T04:50:32Z</dc:date>
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