<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic i.MX6 ULL powerdown sequence in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162161#M162850</link>
    <description>&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;Tell me more about why you have to follow the power-down sequence.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tell us more about what's happening on your device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Do I need to protect it for software termination?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Will it be damaged by the backflow of voltage in the device?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 02 Oct 2020 07:32:26 GMT</pubDate>
    <dc:creator>ban45</dc:creator>
    <dc:date>2020-10-02T07:32:26Z</dc:date>
    <item>
      <title>i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162161#M162850</link>
      <description>&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;Tell me more about why you have to follow the power-down sequence.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tell us more about what's happening on your device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Do I need to protect it for software termination?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Will it be damaged by the backflow of voltage in the device?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 02 Oct 2020 07:32:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162161#M162850</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-02T07:32:26Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162198#M162852</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; the issue has been mainly discussed in&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Power-Down-Sequence-i-MX6ULL/td-p/1159053" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/i-MX-Processors/Power-Down-Sequence-i-MX6ULL/td-p/1159053&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; Incorrect power down sequence may affect i.MX6 lifetime.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Generally it is possible to turn off the power at the same time, assuming the i.MX6 SRTC&lt;BR /&gt;is not used. I do not think, that the i.MX6 lifetime will be affected significantly in such case.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Nevertheless, to be fully on safe side - recommended power up / down sequence should be &lt;BR /&gt;followed.&lt;/P&gt;</description>
      <pubDate>Fri, 02 Oct 2020 08:54:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162198#M162852</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-02T08:54:31Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162647#M162878</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;I would like to know what happens if VDD_SOC_IN and VDD_HIGH_IN are swapped.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Is it okay to drop A and B at the same time?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It is said that the life will be shortened.&lt;/SPAN&gt; &lt;SPAN&gt;Please tell me the reason for the shortening.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 05 Oct 2020 00:04:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162647#M162878</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-05T00:04:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162704#M162884</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; i.MX 6ULL is i.MX 6UL derivative. IMX 6UL till rev. 1.2 has the following issue:&lt;BR /&gt;SNVS_LP registers may be reset during system power down or power up.&lt;BR /&gt;The i.MX 6ULL is not affected, but the requirement VDD_HIGH_IN power down&lt;BR /&gt;is earlier than VDD_SOC_IN concerns the erratum.&lt;BR /&gt;&amp;nbsp; In general, from the Datasheet:&amp;nbsp;&lt;BR /&gt;&lt;EM&gt;The system design must comply with power-up sequence, power-down sequence, and steady state&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;• Excessive current during power-up phase&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;• Prevention of the device from booting&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;• Irreversible damage to the processor (worst-case scenario)&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Mon, 05 Oct 2020 04:46:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1162704#M162884</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-05T04:46:11Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1163830#M163026</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;It was not mentioned in Chip Errata for the i.MX 6ULL.&lt;/P&gt;&lt;P&gt;But,There was a description in Chip Errata for the i.MX 6UltraLite.&lt;/P&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;Can I refer to Chip Errata for the i.MX 6UltraLite and use the &amp;nbsp;i.MX 6ULL?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;There was the following description(Errata for the i.MX 6UltraLite).&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.&lt;BR /&gt;• VDD_HIGH_IN voltage power is less than or equal to 3.0 V.)&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&lt;SPAN class="tlid-translation translation"&gt;&lt;SPAN&gt;Does this mean that the power down sequence sets VDD_HIGH_IN to less than 3.0V before the VDD_SOC voltage drop?&lt;BR /&gt;Is it necessary to reduce VDD_HIGH_IN to 0V?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;Isn't the PMIC configurable time of 2ms irrelevant?&lt;/DIV&gt;&lt;DIV class="result-shield-container tlid-copy-target"&gt;&amp;nbsp;&lt;/DIV&gt;</description>
      <pubDate>Wed, 07 Oct 2020 09:52:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1163830#M163026</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-07T09:52:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1163835#M163028</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I mentioned the i.MX 6UL erratum just to explain why the restriction regarding voltage's&lt;BR /&gt;up / down sequence takes place. The i.MX 6UL erratum is not actual for i.MX 6ULL,&lt;BR /&gt;but power up /down sequence - does.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Wed, 07 Oct 2020 10:11:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1163835#M163028</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-07T10:11:40Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1164267#M163082</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;Is time irrelevant if the order of VDD_SOC_IN and VDD_HIGH_IN is followed?&lt;BR /&gt;What is the voltage that VDD_SOC_IN and VDD_HIGH_IN must hold?&lt;/P&gt;</description>
      <pubDate>Thu, 08 Oct 2020 02:54:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1164267#M163082</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-08T02:54:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1164275#M163085</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Yes, in some sense timings are&amp;nbsp; irrelevant, assuming reasonable boot timings.&lt;BR /&gt;The voltage specs may be found in the i.MX 6ULL Datasheet(s).&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 08 Oct 2020 03:04:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1164275#M163085</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-08T03:04:32Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1165959#M163303</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;Should I keep the following voltage range in the fall sequence?&lt;/P&gt;&lt;P&gt;VDD_SOC_IN&amp;nbsp; is&amp;nbsp; 1.325V&lt;/P&gt;&lt;P&gt;VDD_HIGH_IN is 2.8V&lt;/P&gt;&lt;P&gt;Is it okay？ VDD_HIGH_IN is higher than 2.8V when VDD_SOC_IN is 1.325V or less.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;</description>
      <pubDate>Mon, 12 Oct 2020 09:05:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1165959#M163303</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-12T09:05:27Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1166496#M163372</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; During normal operations power supply voltages should be in range, &lt;BR /&gt;specified in "Operating Ranges" table of i.Mx 6ULL DataSheet. &lt;BR /&gt;VDD_SOC_IN of 1.325V and VDD_HIGH_IN of 2.8V satisfy specs.&lt;BR /&gt;&amp;nbsp;&amp;nbsp; During power-down the voltages will decrease.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Tue, 13 Oct 2020 05:55:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1166496#M163372</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-13T05:55:23Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1167418#M163456</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;Suppose the SNVS power is off in the power down sequence&lt;BR /&gt;Do I need to maintain the order of VDD_SOC_IN and VDD_HIGH_IN? In the data sheet, it seems to affect the registers held by the SNVS power supply. Isn't the order affected if the SNVS power is off?&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2020 11:19:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1167418#M163456</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-14T11:19:49Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1167912#M163491</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;Let me emphasize two points.&lt;/P&gt;
&lt;P&gt;1.&lt;BR /&gt;&amp;nbsp; To be fully on safe side - for applications, where highest reliability &lt;BR /&gt;is the most important - power up/down sequence requirements must be satisfied.&lt;/P&gt;
&lt;P&gt;2.&lt;BR /&gt;&amp;nbsp;&amp;nbsp; In general - for consumer application - it is possible to turn off the power at the same time.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 15 Oct 2020 02:56:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1167912#M163491</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-15T02:56:47Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1168132#M163507</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;&amp;gt;2.&lt;BR /&gt;&amp;gt;&amp;nbsp; &amp;nbsp;In general - for consumer application - it is possible to turn off the power at the same time.&lt;/P&gt;&lt;P&gt;How much timing shift can I tolerate if the power is turned off at the same time (VDD_SOC_IN, VDD_HIGH_IN)?&lt;BR /&gt;It may shift due to the decoupling capacitor and current consumption.&lt;BR /&gt;How many milliseconds can the deviation be tolerated?&lt;BR /&gt;In the event of a power outage, the power will be turned off.&lt;BR /&gt;SNVS is a power source from the PMIC.&lt;BR /&gt;In that case, is it okay to think that the power is turned off at the same time?&lt;BR /&gt;The application used will be a consumer product.&lt;/P&gt;&lt;P&gt;Best regard.&lt;/P&gt;</description>
      <pubDate>Thu, 15 Oct 2020 09:18:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1168132#M163507</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-15T09:18:35Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1168796#M163572</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; Yes, at the event of a power outage, the power will be turned off,&lt;BR /&gt;and this case we can considered that the power is turned off at the same time.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Fri, 16 Oct 2020 09:40:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1168796#M163572</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-16T09:40:57Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1169281#M163640</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;Could you tell me the difference between highest reliability and Consummer? I am using MCIMX6Y2CVM08AB.&lt;BR /&gt;I thought it was a consumer&amp;nbsp; because it was a consumer product.&lt;BR /&gt;Is it right?&lt;/P&gt;&lt;P&gt;best regard.&lt;/P&gt;</description>
      <pubDate>Mon, 19 Oct 2020 03:28:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1169281#M163640</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-19T03:28:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1169384#M163654</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; requirements regarding safety and reliability are application dependent,&lt;BR /&gt;and devices used in design should meet corresponding requirements.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/company/our-company/quality/product-qualification:QUALITY__QUALIF" target="_blank" rel="noopener"&gt;https://www.nxp.com/company/our-company/quality/product-qualification:QUALITY__QUALIF&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Mon, 19 Oct 2020 07:05:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1169384#M163654</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-19T07:05:51Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1174332#M164151</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I would like to ask about the points you answered .&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;gt;In general - for consumer application - it is possible to turn off the power at the same time.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;What kind of consumer application can be considered?&lt;BR /&gt;Is it for factories or homes?&lt;BR /&gt;Could you tell me.&lt;/P&gt;&lt;P&gt;We consider space and aviation to be highly accurate.&lt;BR /&gt;Would you please teach me how to divide it?&lt;/P&gt;&lt;P&gt;best regard&lt;/P&gt;</description>
      <pubDate>Wed, 28 Oct 2020 07:49:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1174332#M164151</guid>
      <dc:creator>ban45</dc:creator>
      <dc:date>2020-10-28T07:49:06Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 ULL powerdown sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1174348#M164154</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172436"&gt;@ban45&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; When designing, engineers must analyze their system: what occurs in case of unexpected crash (software, or power off).&amp;nbsp; Is such situation dangerous for people and other systems? Consumer applications do not require very strong conditions here.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Wed, 28 Oct 2020 08:06:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-ULL-powerdown-sequence/m-p/1174348#M164154</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-10-28T08:06:43Z</dc:date>
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  </channel>
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