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    <title>topic Re: Abouth Flexspi Pin Configuration in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1159180#M162535</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;Thanks for your detailed and understandable reply.&lt;/P&gt;&lt;P&gt;We missed the Table 74. We will not able to&amp;nbsp; use d2 and d3 pinsto boot on the pins ı have already specified.&lt;/P&gt;&lt;P&gt;Kind Regards,&lt;/P&gt;&lt;P&gt;Kaan.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 25 Sep 2020 08:09:06 GMT</pubDate>
    <dc:creator>omerkaanbasakin</dc:creator>
    <dc:date>2020-09-25T08:09:06Z</dc:date>
    <item>
      <title>Abouth Flexspi Pin Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1157914#M162398</link>
      <description>&lt;P&gt;Hello we are using IMXRT-1052 on custom board. Also we are using MCUXpresso IDE and PE Micro UniversalMutilink&amp;nbsp; for debugging. On the custom board we used IS25LP064A as&amp;nbsp; external flash. We want connect flash&amp;nbsp; to mcu from the following pins:&lt;/P&gt;&lt;P&gt;GPIO_SD_B1_06 -&amp;gt; FlexSPI_SSO&amp;nbsp; -&amp;gt; FLEXSPI_A_SSO_B&lt;/P&gt;&lt;P&gt;GPIO_SD_B1_07 -&amp;gt; FlexSPI_CLK -&amp;gt;&amp;nbsp;FLEXSPI_A_SCLK&lt;/P&gt;&lt;P&gt;GPIO_SD_B1_08 -&amp;gt; FlexSPI_DO&amp;nbsp; -&amp;gt;&amp;nbsp;FLEXSPI_A_DATA0&lt;/P&gt;&lt;P&gt;GPIO_SD_B1_09 -&amp;gt; FlexSPI_D1 -&amp;gt;&amp;nbsp; FLEXSPI_A_DATA1&lt;/P&gt;&lt;P&gt;GPIO_AD_B1_11 -&amp;gt; FlexSPI_D2 -&amp;gt;&amp;nbsp;FLEXSPI_A_DATA2&lt;/P&gt;&lt;P&gt;GPIO_AD_B1_10 -&amp;gt; FlexSPI_D3 -&amp;gt;&amp;nbsp;FLEXSPI_A_DATA3&lt;/P&gt;&lt;P&gt;1) What is the meaning of the naming FLEXSPI_A_SSO_B ?&amp;nbsp; It is obvious that this pin is used for FlexSPI_A but what is the meaning of "_B"? Another feature?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2) Can non-sequential FexSPI pins be used&amp;nbsp; ( D2 and D3&amp;nbsp; are sequential&amp;nbsp; but separate from other pins)? If it can, will it effect the flash boot process or flash speed?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind Regards.&lt;/P&gt;</description>
      <pubDate>Wed, 23 Sep 2020 16:30:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1157914#M162398</guid>
      <dc:creator>omerkaanbasakin</dc:creator>
      <dc:date>2020-09-23T16:30:44Z</dc:date>
    </item>
    <item>
      <title>Re: Abouth Flexspi Pin Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1158463#M162453</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/173655"&gt;@omerkaanbasakin&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;Use Table 74 (Boot through FlexSPI) of the Datasheet &lt;BR /&gt;for selecting pins, used for boot. (Looks like FLEXSPI_A_DATA2 and &lt;BR /&gt;FLEXSPI_A_DATA3 are mixed up in Your configuration) &lt;BR /&gt;&lt;BR /&gt;&lt;A href="https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;"_B" suffix means active LOW signal.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Sep 2020 07:42:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1158463#M162453</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-09-24T07:42:36Z</dc:date>
    </item>
    <item>
      <title>Re: Abouth Flexspi Pin Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1159180#M162535</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;Thanks for your detailed and understandable reply.&lt;/P&gt;&lt;P&gt;We missed the Table 74. We will not able to&amp;nbsp; use d2 and d3 pinsto boot on the pins ı have already specified.&lt;/P&gt;&lt;P&gt;Kind Regards,&lt;/P&gt;&lt;P&gt;Kaan.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Sep 2020 08:09:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Abouth-Flexspi-Pin-Configuration/m-p/1159180#M162535</guid>
      <dc:creator>omerkaanbasakin</dc:creator>
      <dc:date>2020-09-25T08:09:06Z</dc:date>
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