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    <title>i.MX ProcessorsのトピックRe: imx6 boot from eFuses</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1156186#M162186</link>
    <description>&lt;P&gt;1. If you plan to use the Linux BSP by NXP, you can use the procedure, described in the "Downloading images using U-Boot" section of the corresponding i.MX Linux User's Guide document.&lt;/P&gt;
&lt;P&gt;Otherwise, you have two options as follows:&lt;/P&gt;
&lt;P&gt;- add a simple switch to your hardware to be able to switch the BOOT_MODE[1:0] signals to 01 to boot the processor in the Serial Downloader mode, then use the regualr procedure with UUU tool;&lt;BR /&gt;- use an external eMMC programming tool.&lt;/P&gt;
&lt;P&gt;2. There is no problem to use these pins for CSI function as you describe.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;</description>
    <pubDate>Mon, 21 Sep 2020 09:48:58 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2020-09-21T09:48:58Z</dc:date>
    <item>
      <title>imx6 boot from eFuses</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1153438#M161832</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am planning to configure imx6 into a boot from eMMC always.&lt;/P&gt;&lt;P&gt;my configuration is&lt;/P&gt;&lt;P&gt;BOOT_MODE[1:0] set always 00.&lt;/P&gt;&lt;P&gt;and I will burn the&amp;nbsp;BT_FUSE_SEL into 1, efuses accordingly to boot from eMMC.&lt;/P&gt;&lt;P&gt;So now my questions are,&lt;/P&gt;&lt;P&gt;1. Is it possible to reflash the eMMC later as my firmware changes? if yes please let me know the procedure?&lt;/P&gt;&lt;P&gt;2. I want to interface 2 parallel cameras (10bit mode) into imx6&lt;/P&gt;&lt;P&gt;Camera1 pin connections I have no issues.&lt;/P&gt;&lt;P&gt;Camera 2 pin connection I have added here, in this pins list few pins are shared with boot configuration pins.&lt;/P&gt;&lt;P&gt;is there a problem if I use these pins to connect my camera. anyways I am planning boot from eFuses.&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA10&lt;/TD&gt;&lt;TD&gt;EIM_EB1&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA11&lt;/TD&gt;&lt;TD&gt;EIM_EB0&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA12&lt;/TD&gt;&lt;TD&gt;EIM_A17&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA13&lt;/TD&gt;&lt;TD&gt;EIM_A18&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA14&lt;/TD&gt;&lt;TD&gt;EIM_A19&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA15&lt;/TD&gt;&lt;TD&gt;EIM_A20&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA16&lt;/TD&gt;&lt;TD&gt;EIM_A21&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA17&lt;/TD&gt;&lt;TD&gt;EIM_A22&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA18&lt;/TD&gt;&lt;TD&gt;EIM_A23&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA19&lt;/TD&gt;&lt;TD&gt;EIM_A24&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_HSYNC&lt;/TD&gt;&lt;TD&gt;EIM_DA11&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_VSYNC&lt;/TD&gt;&lt;TD&gt;EIM_DA12&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_PIXCLK&lt;/TD&gt;&lt;TD&gt;EIM_A16&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;IPU2_CSI1_DATA_EN&lt;/TD&gt;&lt;TD&gt;EIM_DA10&lt;/TD&gt;&lt;TD&gt;(ALT2)&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Sep 2020 10:39:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1153438#M161832</guid>
      <dc:creator>santhosh205415</dc:creator>
      <dc:date>2020-09-15T10:39:31Z</dc:date>
    </item>
    <item>
      <title>Re: imx6 boot from eFuses</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1156186#M162186</link>
      <description>&lt;P&gt;1. If you plan to use the Linux BSP by NXP, you can use the procedure, described in the "Downloading images using U-Boot" section of the corresponding i.MX Linux User's Guide document.&lt;/P&gt;
&lt;P&gt;Otherwise, you have two options as follows:&lt;/P&gt;
&lt;P&gt;- add a simple switch to your hardware to be able to switch the BOOT_MODE[1:0] signals to 01 to boot the processor in the Serial Downloader mode, then use the regualr procedure with UUU tool;&lt;BR /&gt;- use an external eMMC programming tool.&lt;/P&gt;
&lt;P&gt;2. There is no problem to use these pins for CSI function as you describe.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;</description>
      <pubDate>Mon, 21 Sep 2020 09:48:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1156186#M162186</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2020-09-21T09:48:58Z</dc:date>
    </item>
    <item>
      <title>Re: imx6 boot from eFuses</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1156217#M162192</link>
      <description>&lt;P&gt;Thank you for your support.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Sep 2020 10:53:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-boot-from-eFuses/m-p/1156217#M162192</guid>
      <dc:creator>santhosh205415</dc:creator>
      <dc:date>2020-09-21T10:53:06Z</dc:date>
    </item>
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