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    <title>topic Re: Communication Latency between A53 and M4. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1155128#M162059</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;What Kernel version and Yocto release are you using?&lt;/P&gt;</description>
    <pubDate>Fri, 18 Sep 2020 01:32:23 GMT</pubDate>
    <dc:creator>fabianmpa019</dc:creator>
    <dc:date>2020-09-18T01:32:23Z</dc:date>
    <item>
      <title>Communication Latency between A53 and M4.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1012988#M150025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, i have imx8m mini evk and i have tested communication between A53 and M4 using RPMsg. I would like to know the methods that can be used to measure communication latency between A53 and M4?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&amp;nbsp;&lt;/P&gt;&lt;P&gt;Noufal P&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Nov 2019 12:44:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1012988#M150025</guid>
      <dc:creator>noufal_p</dc:creator>
      <dc:date>2019-11-06T12:44:53Z</dc:date>
    </item>
    <item>
      <title>Re: Communication Latency between A53 and M4.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1012989#M150026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunately, it could be possible, but it will not be an easy task.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you go to the MU part of the reference manual, you can find that there is a flag that changes the state when the transmission between cores is finished. You will need to create a code in the M4 cortex that could detect when the flag changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The name of the register is&amp;nbsp;Processor x Status Register (MUx_ASR).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, in the code, you will need to play with the timers and interrupts to handle this operation. Unfortunately, this is out of our scope.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I apologize for the inconvenience this may give you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Diego.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Nov 2019 23:05:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1012989#M150026</guid>
      <dc:creator>diegoadrian</dc:creator>
      <dc:date>2019-11-22T23:05:30Z</dc:date>
    </item>
    <item>
      <title>Re: Communication Latency between A53 and M4.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1155128#M162059</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;What Kernel version and Yocto release are you using?&lt;/P&gt;</description>
      <pubDate>Fri, 18 Sep 2020 01:32:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Communication-Latency-between-A53-and-M4/m-p/1155128#M162059</guid>
      <dc:creator>fabianmpa019</dc:creator>
      <dc:date>2020-09-18T01:32:23Z</dc:date>
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