iMX8MM MIPI-CSI clock properties setting

khang_letruong — Fri, 11 Sep 2020 10:38:13 GMT

Hi All,

I'm integrating an existing driver for Sony IMX296 sensor using the patch from here : https://patchwork.kernel.org/cover/11219369/

In the device-tree, I modified the following OV5640 sensor node :

ov5640_mipi: ov5640_mipi@3c { compatible = "ovti,ov5640_mipi"; reg = <0x3c>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; clocks = <&clk IMX8MM_CLK_CLKO1>; clock-names = "csi_mclk"; assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; assigned-clock-parents = <&clk IMX8MM_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; mclk = <24000000>; mclk_source = <0>; port { ov5640_mipi1_ep: endpoint { remote-endpoint = <&mipi1_sensor_ep>; }; }; };

imx296_mipi: imx296_mipi@1a { compatible = "sony,imx296_mipi"; reg = <0x1a>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; clocks = <&clk IMX8MM_CLK_CSI1_CORE>; clock-names = "csi_mclk"; clock-frequency = <37125000>; assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; assigned-clock-rates = <37125000>; mclk = <37125000>; mclk_source = <0>; csi_id = <0>; rst-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; //vddo-supply = <&reg_camera_board_1p8v>; //vdda-supply = <&reg_camera_board_3p3v>; //vddd-supply = <&reg_camera_board_1p2v>; port { imx296_mipi1_ep: endpoint { remote-endpoint = <&mipi1_sensor_ep>; }; }; };

Among the clock properties, I could see that clock-name and clock-frequency are used in the sensor driver's source code. However, it is not quite clear for me the relationship btw clocks, assigned-clocks, assigned-clock-parents, assigned-clock-rates. I would really appreciate if anyone can explain me more, please ?

Also, as the IMX296 sensor requires 37125000 Hz as clock source, I modified assigned-clock-parents from <&clk IMX8MM_CLK_24M> to <&clk IMX8MM_SYS_PLL1_266M> since from this thread, it is said that "using IMX8MM_CLK_24M [24MHz] as parent seems it is not possible to derive from it 50MHz, assigned-clock-rates = <0>, <50000000>;"

Moreover, I modified clocks and assigned-clocks to IMX8MM_CLK_CSI1_CORE (instead of IMX8MM_CLK_CLKO1 or IMX8MM_CLK_CLKO1_DIV) and I think more logical for CSI interface, do you agree ?

Thanks in advance for your opinion and best regards,

Khang

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