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    <title>topic Re: imx6ull SPI Performance issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151490#M161585</link>
    <description>&lt;P&gt;Thanks for your quick response.&lt;/P&gt;&lt;P&gt;When we are setting frequency to 5MHZ and we are able to receive 300 data packets per second but with 18MHZ we are getting only 150 data packets. Could you please tell us the reason behind this drop.&lt;/P&gt;</description>
    <pubDate>Thu, 10 Sep 2020 09:26:03 GMT</pubDate>
    <dc:creator>sheik</dc:creator>
    <dc:date>2020-09-10T09:26:03Z</dc:date>
    <item>
      <title>imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151033#M161521</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are using 4.1.15 linux kernel on imx6ull platform.&lt;/P&gt;&lt;P&gt;We are facing below issues in our platform,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;1.when we are testing with SPI data transfer we observed there is a huge delay ( ~9.5us ) between chip select and MOSI line . Even after data transmission there is huge delay( ~35 us ) in making the chip select high. Please let us know how to reduce this delays in kernel. Please find the attached Logic analyzer image.&lt;BR /&gt;2.Also, we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ, throughput is very less in 18MHZ compared to 5MHZ.Please where to find patches to increase the throughput in linux kernel.&amp;nbsp;&lt;BR /&gt;3. Presently we are using PIO for data transfer. please let me know, were we will find the patches to enable/configure DMA &amp;amp; Burst transfer in SPI.&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Sheik&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 09 Sep 2020 16:28:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151033#M161521</guid>
      <dc:creator>sheik</dc:creator>
      <dc:date>2020-09-09T16:28:38Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151158#M161532</link>
      <description>&lt;P&gt;Hi Sheik&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;- one can try patch for eCSPI native CS lines&lt;/P&gt;
&lt;P&gt;&lt;A href="https://patchwork.kernel.org/patch/10044381/" target="_blank"&gt;https://patchwork.kernel.org/patch/10044381/&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;-&amp;nbsp; use dts "dmas" :&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt?h=imx_4.1.15_2.0.0_ga" target="_blank"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt?h=imx_4.1.15_2.0.0_ga&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;CODE&gt;&lt;/CODE&gt;&lt;/P&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Wed, 09 Sep 2020 23:27:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151158#M161532</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-09-09T23:27:40Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151319#M161565</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;1.As you suggested to apply the below patches is already taken care in our spi-imx.c driver, please refer the attached driver for your reference&lt;BR /&gt;2.Also we are using "dmas" in our dts file.&lt;/P&gt;&lt;P&gt;Below are the dts changes we have done in our side,&lt;BR /&gt;&lt;BR /&gt;ecspi1: ecspi@02008000 {&lt;BR /&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;BR /&gt;compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";&lt;BR /&gt;reg = &amp;lt;0x02008000 0x4000&amp;gt;;&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clks IMX6UL_CLK_ECSPI1&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clks IMX6UL_CLK_ECSPI1&amp;gt;;&lt;BR /&gt;clock-names = "ipg", "per";&lt;BR /&gt;dmas = &amp;lt;&amp;amp;sdma 3 7 1&amp;gt;, &amp;lt;&amp;amp;sdma 4 7 2&amp;gt;;&lt;BR /&gt;dma-names = "rx", "tx";&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;3.I have attached our spi-imx.c driver file for your reference.&lt;/P&gt;&lt;P&gt;Please provide us any other suggestion so that we could able to improve SPI performance.&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 06:12:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151319#M161565</guid>
      <dc:creator>sheik</dc:creator>
      <dc:date>2020-09-10T06:12:05Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151350#M161568</link>
      <description>&lt;P&gt;unfortunately&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;it is not possible to further reduce these delays,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;as it is defined in hardware (hardware limitation).&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards&lt;BR /&gt;igor&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 06:35:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151350#M161568</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-09-10T06:35:22Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151438#M161580</link>
      <description>&lt;P&gt;Thank you for valuable input. We understood the limitation in chip-select.&lt;/P&gt;&lt;P&gt;we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ, throughput is very less in 18MHZ compared to 5MHZ.Please let us know what could be the reason behind this and also patches to increase the throughput in linux kernel if available.&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 08:23:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151438#M161580</guid>
      <dc:creator>sheik</dc:creator>
      <dc:date>2020-09-10T08:23:30Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151467#M161582</link>
      <description>&lt;P&gt;&amp;gt;&lt;SPAN&gt;we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ, &lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;gt;throughput is very less in 18MHZ compared to 5MHZ.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mentioned delays are caused by internal processor delays, not related directly to&amp;nbsp;SPI clock frequency.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards&lt;BR /&gt;igor&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 08:53:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151467#M161582</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-09-10T08:53:16Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151490#M161585</link>
      <description>&lt;P&gt;Thanks for your quick response.&lt;/P&gt;&lt;P&gt;When we are setting frequency to 5MHZ and we are able to receive 300 data packets per second but with 18MHZ we are getting only 150 data packets. Could you please tell us the reason behind this drop.&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 09:26:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151490#M161585</guid>
      <dc:creator>sheik</dc:creator>
      <dc:date>2020-09-10T09:26:03Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ull SPI Performance issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151551#M161594</link>
      <description>&lt;P&gt;&amp;gt;Could you please tell us the reason behind this drop&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;please recheck ecspi settings in both cases. Test performance with the same&lt;/P&gt;
&lt;P&gt;settings in both cases.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 11:55:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ull-SPI-Performance-issue/m-p/1151551#M161594</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-09-10T11:55:45Z</dc:date>
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