i.MX ProcessorsのトピックRe: PCIe Bandwidth

PCIe Bandwidth

adamdgray — Tue, 25 Aug 2020 17:20:25 GMT

What bandwidth should we expect to achieve with the I.MX8 PCI-E Gen 2 interface?

Currently, we have a Xilinx Kintex-7 FPGA design and can achieve 2.8 Gbps when transmitting from the I.MX8 to the FPGA and only 2.2 Gbps when receiving from the FPGA to the I.MX8. To achieve the 2.8 Gbps trasmitting rate from the I.MX8 to the FPGA we are using the I.MX8’s PCIe DMA engine.

We would like to achieve above 2.5 Gbps when receiving from the FPGA to the I.MX8. We have tried using the I.MX8’s PCIe DMA engine as well as a DMA engine inside the FPGA with no success. In addition, we have tried pushing test data over the PCIe bus and still the I.MX8 would not accept data faster than 2.2 Gbps.

Re: PCIe Bandwidth

weidong_sun — Wed, 26 Aug 2020 04:08:06 GMT

Hello Adam,

Below is our test result for I.MX8 PCIe:

Two boards, one board PCIe used as EP, the other one PCIe used as RC.

Connect by two board.

Hope the information is helpful to you.

Have a nice day!

B.R,

Weidong

Re: PCIe Bandwidth

adamdgray — Wed, 02 Sep 2020 17:53:51 GMT

Can you clarify the data. Was the Endpoint the master and the RC the slave?

Did you do have any data with other side being the master?

Assuming the End Point is the master for this data, is there a reason the EP can accept data so much faster then the RC?

Re: PCIe Bandwidth

weidong_sun — Tue, 08 Sep 2020 01:57:12 GMT

Hello Adam,

The data is from design team, test diagram is below:

i.MX boar PCIe(RC) <------>i.MX board PCIe(EP)

Hope the information is helpful to you.

Have a nice day!

B.R,

Weidong

Re: PCIe Bandwidth

adamdgray — Tue, 08 Sep 2020 12:03:12 GMT

Sorry, that diagram did not provide any new information.

I am asking you to clarify who was the bus master in the data you provided and if you have any information why the data rate is so much slower in one direction.

Re: PCIe Bandwidth

weidong_sun — Wed, 09 Sep 2020 01:06:30 GMT

Regarding to the PCIe protocol, EP is act as bus master to kick off the data transactions.

RC can't act the master in the EP's data transactions.

Hope the information is helpful to you.

Have a nice day!

B.R,

weidong

Re: PCIe Bandwidth

adamdgray — Wed, 09 Sep 2020 10:32:01 GMT

Do you have any data for the Root Complex transactions?

Re: PCIe Bandwidth

weidong_sun — Thu, 10 Sep 2020 07:15:58 GMT

No, We don't have the benchmark of the RC transactions.

Re: PCIe Bandwidth

jishin42 — Fri, 18 Sep 2020 08:00:36 GMT

The data look promising, but I agree with @adamdgray , it lacks some details :

- Hadware : how was made the connection between the boards ? A cable (which one?) between the M2 slots or a cable/card between the B2B connectors ?

- Software : is it possible to have the BSP used for these tests ?

Best regards

Re: PCIe Bandwidth

Miles_Lee — Fri, 21 Jan 2022 02:52:43 GMT

Hi Weidong,

Does this test data based on read/ write full duples? If no, could you please help provide the maximum bandwidth of read/ write 8M.Mini PCIe at the same time?

BR, thanks.

Miles Lee