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    <title>i.MX Processors中的主题 Re: i.MX 8M Mini CSI camera clock lane</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-CSI-camera-clock-lane/m-p/1146772#M161231</link>
    <description>&lt;P&gt;&lt;STRONG&gt;Q1:&lt;/STRONG&gt; Any ideas what to check?&lt;/P&gt;&lt;P&gt;&amp;gt;you can check if you can get the correct mipi clock or not, like PHY reference clock and clk_ui&lt;/P&gt;&lt;P&gt;Q2,Q3, Q4:&lt;/P&gt;&lt;P&gt;&amp;gt;I got information:"&lt;/P&gt;&lt;P&gt;&lt;FONT color="#0747a6"&gt;&lt;EM&gt;"checked with IP team that we don't have "WCLK_SRC" bit any more.&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#0747a6"&gt;&lt;EM&gt;The original purpose of "WCLK_SRC" is to set clock speed, but it has been removed after fixed it as max speed case internally.we removed "WCLK_SRC" related description from ERR_OVER &lt;/EM&gt;&lt;/FONT&gt;"&lt;/P&gt;&lt;P&gt;Q5:&lt;/P&gt;&lt;P&gt;&amp;gt;yes&lt;/P&gt;&lt;P&gt;Q6:&lt;/P&gt;&lt;P&gt;&amp;gt; I don't know what you mean, if you mean Absolute register address, pls refer to the 13.4.15 MIPI CSI Memory Map/Register Definition of Reference Manual&lt;/P&gt;</description>
    <pubDate>Fri, 04 Sep 2020 07:39:28 GMT</pubDate>
    <dc:creator>joanxie</dc:creator>
    <dc:date>2020-09-04T07:39:28Z</dc:date>
    <item>
      <title>i.MX 8M Mini CSI camera clock lane</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-CSI-camera-clock-lane/m-p/1133800#M160977</link>
      <description>&lt;P&gt;I am running into a problem here: The MIPI clock from a camera sensor is sometimes not detected: Register MIPI_CSI_DPHY_STATUS transitions from Bitfield STOPSTATEDAT 1 to 0 (which is good) but Bitfield STOPSTATECLK remains at 1, which means: "Clock lane is in Stop State".&lt;/P&gt;&lt;P&gt;MIPI_CSIS_DPHYCTRL should be set correctly.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q1:&lt;/STRONG&gt; Any ideas what to check?&lt;/P&gt;&lt;P&gt;In the TRM I cannot find any specific information about specific requirements regarding the clock.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q2:&lt;/STRONG&gt; TRM of i.MX 8M Mini Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 does not describe Bit 0 at all, but TRM of i.mx7 does as WCLK_SRC. Why is that?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q3:&lt;/STRONG&gt; TRM lacks description of WCLK_SRC while referencing WCLK_SRC in some places like MIPI_CSI_INTERRUPT_SOURCE_0 Bit ERR_OVER. Is this a Bug?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q4:&lt;/STRONG&gt; On i.MX 8M Mini the driver sets in Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 Bit Number 0 (WCLK_SRC) to value 1, but reading value of Bit Number 0 back it is a 0. Why is that? Shouldn't it be 1?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q5:&lt;/STRONG&gt; Is MIPI PHY (described in TRM i.MX 8M Mini 13.6.10 MIPI PHY Memory Map/Register Definition) somehow related/connected to the CSI (camera interface)?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q6:&lt;/STRONG&gt; If yes: In TRM i.MX 8M Mini "13.6.10 MIPI PHY Memory Map/Register Definition" I cannot find any absolute register-Address like I do for e.g. MIPI_CSI_DPHY_STATUS = 0x32e30020. What is the absolute register address for the MIPI PHY?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 02 Sep 2020 07:01:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-CSI-camera-clock-lane/m-p/1133800#M160977</guid>
      <dc:creator>honklee</dc:creator>
      <dc:date>2020-09-02T07:01:49Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Mini CSI camera clock lane</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-CSI-camera-clock-lane/m-p/1146772#M161231</link>
      <description>&lt;P&gt;&lt;STRONG&gt;Q1:&lt;/STRONG&gt; Any ideas what to check?&lt;/P&gt;&lt;P&gt;&amp;gt;you can check if you can get the correct mipi clock or not, like PHY reference clock and clk_ui&lt;/P&gt;&lt;P&gt;Q2,Q3, Q4:&lt;/P&gt;&lt;P&gt;&amp;gt;I got information:"&lt;/P&gt;&lt;P&gt;&lt;FONT color="#0747a6"&gt;&lt;EM&gt;"checked with IP team that we don't have "WCLK_SRC" bit any more.&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#0747a6"&gt;&lt;EM&gt;The original purpose of "WCLK_SRC" is to set clock speed, but it has been removed after fixed it as max speed case internally.we removed "WCLK_SRC" related description from ERR_OVER &lt;/EM&gt;&lt;/FONT&gt;"&lt;/P&gt;&lt;P&gt;Q5:&lt;/P&gt;&lt;P&gt;&amp;gt;yes&lt;/P&gt;&lt;P&gt;Q6:&lt;/P&gt;&lt;P&gt;&amp;gt; I don't know what you mean, if you mean Absolute register address, pls refer to the 13.4.15 MIPI CSI Memory Map/Register Definition of Reference Manual&lt;/P&gt;</description>
      <pubDate>Fri, 04 Sep 2020 07:39:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-CSI-camera-clock-lane/m-p/1146772#M161231</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2020-09-04T07:39:28Z</dc:date>
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