topic This an automatic process. We are marking this post as s... in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/1136436#M161157 <B>This an automatic process.</B><BR /><BR /> We are marking this post as solved, due to the either low activity or any reply marked as correct.<BR /><BR /> If you have additional questions, please create a new post and reference to this closed post.<BR /><BR /> NXP Community! Thu, 03 Sep 2020 15:36:12 GMT CommunityBot 2020-09-03T15:36:12Z Deserializer in https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/369325#M52661 <HTML><HEAD></HEAD><BODY><P><SPAN>When</SPAN><SPAN> </SPAN><SPAN>capturing</SPAN><SPAN> </SPAN><SPAN>iMX6D </SPAN><SPAN> </SPAN><SPAN>RGB565</SPAN><SPAN> </SPAN><SPAN>format</SPAN><SPAN> </SPAN><SPAN>via</SPAN><SPAN> the </SPAN><SPAN>deserializer</SPAN><SPAN> </SPAN><SPAN>In</SPAN></P><P><SPAN>What </SPAN><SPAN>is</SPAN><SPAN> the </SPAN><SPAN>signal</SPAN><SPAN> </SPAN><SPAN>assignment</SPAN><SPAN> </SPAN><SPAN>of</SPAN><SPAN> the </SPAN><SPAN>data bus</SPAN><SPAN>.</SPAN></P><P><SPAN>Which corresponding bits to each bit of&nbsp; data bus&nbsp; to&nbsp; R</SPAN><SPAN> </SPAN><SPAN> </SPAN><SPAN>[</SPAN><SPAN>5:00</SPAN><SPAN>]</SPAN><SPAN>,</SPAN><SPAN> G </SPAN><SPAN>[</SPAN><SPAN>5:01</SPAN><SPAN>]</SPAN><SPAN>,</SPAN><SPAN> </SPAN><SPAN>b</SPAN><SPAN> </SPAN><SPAN>[</SPAN><SPAN>5:00</SPAN><SPAN>] </SPAN><SPAN>?</SPAN></P></BODY></HTML> Mon, 06 Oct 2014 04:56:50 GMT https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/369325#M52661 takashitakahash 2014-10-06T04:56:50Z Re: Deserializer in https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/369326#M52662 <HTML><HEAD></HEAD><BODY><P>Hi Takashi</P><P></P><P>MIPI-CSI data bit placement is given in </P><P>sect.40.5.1 General/Arbitrary Data Reception</P><P><A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&amp;WT_TYPE=Reference%20Manuals&amp;WT_VENDOR=FREESCALE&amp;WT_FILE_FORMAT=pdf&amp;WT_ASSET=Documentation&amp;fileExt=.pdf">IMX6DQRM</A> </P><P></P><P>as for CSI bit allocation one can look at</P><P>sect.4.11.10.1 IPU Sensor Interface Signal Mapping</P><P><A href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf?fasp=1&amp;WT_TYPE=Data%20Sheets&amp;WT_VENDOR=FREESCALE&amp;WT_FILE_FORMAT=pdf&amp;WT_ASSET=Documentation&amp;fileExt=.pdf">IMX6DQCEC</A> </P><P></P><P>Best regards</P><P>igor</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Mon, 06 Oct 2014 06:07:55 GMT https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/369326#M52662 igorpadykov 2014-10-06T06:07:55Z This an automatic process. We are marking this post as s... https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/1136436#M161157 <B>This an automatic process.</B><BR /><BR /> We are marking this post as solved, due to the either low activity or any reply marked as correct.<BR /><BR /> If you have additional questions, please create a new post and reference to this closed post.<BR /><BR /> NXP Community! Thu, 03 Sep 2020 15:36:12 GMT https://community.nxp.com/t5/i-MX-Processors/Deserializer-in/m-p/1136436#M161157 CommunityBot 2020-09-03T15:36:12Z