i.MX Processorsのトピックimx6 solox rmii interface bringup issue

imx6 solox rmii interface bringup issue

ramki31 — Thu, 03 Sep 2020 03:43:52 GMT

Hi Nxp,

We are testing a custom imx6 solox processor board with linux kernel 5.4.

We have interfaced i.mx6 solox processor ENET1 and ENET2 with phy(KSZ8081RNB) through RMII Interface. Two ethernet phy used in Design.

We are getting the kernel log stops (Prints are stuck and some junk is displaying).

After removing the resistor r25 and r26 (Phy can source 50MHz Clock) we are able to detect both the phy but the link is not up/ready.

Kindly suggest why we are not able to feed the 50Mhz clk into the ENET1_TX_CLK,ENET2_TX_CLK and how to make the link up ?

Please refer the dts,pin muxing and clk settings we made in the design

NOTE:We have removed the Ethernet phy changes fully in the U-boot. Please tell us whether it is creating any impact?

We have attached the schematic and dts and clock changes we made ,kindly check and let us know if any correction is needed

Re: imx6 solox rmii interface bringup issue

ramki31 — Thu, 03 Sep 2020 03:50:12 GMT

please find the attached dts and clk changes

Re: imx6 solox rmii interface bringup issue

igorpadykov — Thu, 03 Sep 2020 06:51:13 GMT

Hi ramki31

>We have removed the Ethernet phy changes fully in the U-boot.
>why we are not able to feed the 50Mhz clk into the ENET1_TX_CLK,ENET2_TX_CLK and how to make the link up ?

reason may be that clock initialization is performed in uboot, IOMUXC_GPR_GPR1 register

function setup_fec()

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6sxsabresd/mx6sxsabresd.c?h=imx_v2020.04_5.4.24_2.1.0

Best regards
igor