<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: imx6dl external asynchronous SRAM</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091962#M159991</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ok so this has to be a hardware change in&amp;nbsp; my scenario&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 26 Jun 2020 02:40:06 GMT</pubDate>
    <dc:creator>shashikanthirem</dc:creator>
    <dc:date>2020-06-26T02:40:06Z</dc:date>
    <item>
      <title>imx6dl external asynchronous SRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091960#M159989</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have one doubt&amp;nbsp; on&amp;nbsp;imx6dl platform&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;do we have&amp;nbsp;&amp;nbsp;EIM_LBA&amp;nbsp;polarity configurable ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note:&lt;/P&gt;&lt;P&gt;as &lt;SPAN&gt;EIM_LBA&lt;/SPAN&gt; pin is connected to external SRAM latch pin which is a active high signal,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ideally we should have put a NOT gate between&amp;nbsp;&lt;SPAN&gt;EIM_LBA&amp;nbsp; and&amp;nbsp;Latch Enable pin of ext SRAM&lt;/SPAN&gt;&amp;nbsp;, as this&amp;nbsp;&lt;SPAN&gt;EIM_LBA is active low, make ADDR to get latch this pin will be ZERO, but our ext SRAM latch pin is active HIGH, which does not&amp;nbsp;work at all,&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;guys any input&amp;nbsp;on work around on software without making hardware change.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jun 2020 20:27:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091960#M159989</guid>
      <dc:creator>shashikanthirem</dc:creator>
      <dc:date>2020-06-25T20:27:03Z</dc:date>
    </item>
    <item>
      <title>Re: imx6dl external asynchronous SRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091961#M159990</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi shashikant&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;do we have&amp;nbsp;&amp;nbsp;EIM_LBA&amp;nbsp;polarity configurable ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately not, polarity is not configurable.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jun 2020 23:41:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091961#M159990</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-06-25T23:41:37Z</dc:date>
    </item>
    <item>
      <title>Re: imx6dl external asynchronous SRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091962#M159991</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ok so this has to be a hardware change in&amp;nbsp; my scenario&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Jun 2020 02:40:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6dl-external-asynchronous-SRAM/m-p/1091962#M159991</guid>
      <dc:creator>shashikanthirem</dc:creator>
      <dc:date>2020-06-26T02:40:06Z</dc:date>
    </item>
  </channel>
</rss>

