topic I.MX6QP mipi csi2 error in i.MX Processors

I.MX6QP mipi csi2 error

eason-tang — Thu, 13 Aug 2020 11:28:29 GMT

Hi,

i was developing a camera-surround project.

My hardware environment is IMX6QP+TIUB964+TIUB933+OVOX1F and MIPI 4 lanes + YUV422 ;

When i opened V4L2 device,the mipi csi2 log showed as below:

mipi csi2 dphy status mipi_reg 0x300!

mipi csi2 error1 mipi_reg 0x11000000!

mipi csi2 error2 mipi_reg 0x100!

mipi csi2 can not reveive data correctly!

I have viewed the reference documents that

CSI ERROR1

Bit28.
err_ecc_double
Header ECC contains 2 errors. Unrecoverable.
Default Value: 0
Bit24.
vc0_err_crc
Checksum Error detected on Virtual Channel 0
Default Value: 0

CSI ERROR2

Bit8.
vc0_err_ecc
corrected
Header error detected and corrected on Virtual Channel 0
Default Value: 0

But TIUB964+TIUB933+OVOX1F which connected to my internal platform could receive image data successfully;

So what is the next way to solve this issue ?

Is this a TI UB964 configure issue ?

Re: I.MX6QP mipi csi2 error

igorpadykov — Fri, 14 Aug 2020 00:05:32 GMT

Hi Qingcai

one can look at below examples which may help

https://community.nxp.com/docs/DOC-102233

iMX6DQ MAX9286 MIPI CSI2 720P camera surround view solution for Linux BSP

Best regards
igor
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Re: I.MX6QP mipi csi2 error

eason-tang — Fri, 14 Aug 2020 03:09:37 GMT

Hi igorpadykov‌:

Thanks for your reply.

I will review that examples and patches first.

And i want to know how to debug this issue?

Is this a mipi-csi2-freq mismatch issue ?

Re: I.MX6QP mipi csi2 error

igorpadykov — Fri, 14 Aug 2020 10:25:59 GMT

yes this also may be the reason, one can look at sect.3.4. MIPI D-PHY clock

AN5305 MIPI–CSI2 Peripheral on i.MX6 MPUs

Best regards
igor

Re: I.MX6QP mipi csi2 error

eason-tang — Mon, 17 Aug 2020 02:22:24 GMT

Hi igorpadykov‌

Thanks for your reply.

I have solved my issue by reading "Debug steps for customer MIPI sensor.docx".

Thank you very much.