topic Re: IMX7DRM Memory map/register definition in i.MX Processors

IMX7DRM Memory map/register definition

andreas_vorderl — Wed, 29 Apr 2020 08:53:00 GMT

Hi,

I am trying to port the ethernet interface to FreeRTOS and I am now in the process of creating various data structures to represent the memory map/registers.
However, I found some differences between the bit definition of almost all registers in the MCIMX7D_M4.h (https://www.nxp.com/webapp/Download?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=license ) file and the IMX7DRM reference manual (Rev. 1, 01/2018) (https://www.nxp.com/webapp/Download?colCode=IMX7DRM ). E.g. following register: 11.1.5.9 Receive Control Register (ENETx_RCR).

It would be greate to know if the reference manual is correct or the original MCIMX7D_M4.h file. In detail, in the file MCIMX7D_M4.h bit 0 has been exchanged to bit 31. And vice versa.

Thanks in advance.

Best regards,
Andreas

Re: IMX7DRM Memory map/register definition

Yuri — Wed, 29 Apr 2020 10:08:51 GMT

Hello,

The following Community thread can clarify the issue.

https://community.nxp.com/message/1178838

Regards,

Yuri.

Re: IMX7DRM Memory map/register definition

andreas_vorderl — Wed, 29 Apr 2020 12:13:47 GMT

Hi,

thanks a lot,
but why are these registers defined in big endian? The registers are defined in the same way for i.MX6 and i.MX8. Only the i.MX7 is different.

Regards,
Andreas

Re: IMX7DRM Memory map/register definition

Yuri — Thu, 30 Apr 2020 04:01:46 GMT

Hi,

the MCIMX7D_M4.h file is correct: I mean bit masks for registers bit fields.

Regards,

Yuri.