topic Re: About ADC channel assignment in i.MX Processors

About ADC channel assignment

goto11 — Fri, 29 May 2020 06:35:39 GMT

Hello,Community

Assigned to ADC1_IN0 to ADC1_IN3 in Table 99 of the data sheet.

On the other hand, in the ADC memory map of Reference Manual, ADC1 has CH_A to CH_D.
Is it possible to assign Channel 0 to CHA_SEL, Channel 1 to CHB_SEL, Channel 2 to CHC_SEL, and Channel 3 to CHD_SEL to support the following?

IN0-CH_A
IN1-CH_B
IN2-CH_C
IN3-CH_D

best regards

Goto

Re: About ADC channel assignment

igorpadykov — Fri, 29 May 2020 10:49:50 GMT

Hi Goto

yes this is possible. As described in sect.14.1.1 Overview

i.MX 7Dual Applications Processor Reference Manual

"ADC supports conversion up to five logic groups (ChA /
ChB / ChC / ChD / SW). Each group can select one channel
from 0 - 15 physical channels."

Best regards
igor
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About ADC channel assignment

tamotsu — Thu, 13 Nov 2025 07:16:42 GMT

Hello igorpadykov.

This is a solution, but I don't understand it, so I have a question.

According to the pin assignment in the datasheet, there are eight physical inputs, ADC1_IN0 to ADC2_IN3.

In the reference manual, CHA_SEL of ADCx_CH_A_CFG1 ranges from 0 to 15.

What do ADC1_INx and Channelx correspond to?
Or are they unrelated?

How should I set ADC2_IN0?

Best regards.