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    <title>topic Re: The relation between ARM Cortex A53 64-bit and LPDDR4 16-bit in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087348#M159375</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Internal details of i.MX8Mn are not provided. Nevertheless, because of internal DDRC buffer(s)&lt;/P&gt;&lt;P&gt;it is possible to avoid performance issues.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 14 Apr 2020 09:39:01 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2020-04-14T09:39:01Z</dc:date>
    <item>
      <title>The relation between ARM Cortex A53 64-bit and LPDDR4 16-bit</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087347#M159374</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&amp;nbsp;&lt;/P&gt;&lt;P&gt;This question refers to the I.MX8 nano which is based on ARM Cortex A-53.&lt;/P&gt;&lt;P&gt;I would like to get a better understanding regarding the relation between the core (ARM Cortex A53 64-bit) and the external memory LPDDR4 from performance perspective.&lt;/P&gt;&lt;P&gt;According to &lt;EM&gt;i.MX 8M Nano Applications Processor Reference Manual&lt;/EM&gt; document (Document Number: IMX8MNRM&lt;/P&gt;&lt;P&gt;Rev. 0, 12/2019), the DRAM controller and PHY includes:&amp;nbsp;&lt;/P&gt;&lt;P&gt;• LPDDR4-3200, DDR4-2400, and DDR3L-1600 in Non-POP BGA package&lt;BR /&gt;• 16-bit DRAM interface&lt;BR /&gt;• 800MHz 64-bit AXI bus&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let's assume&amp;nbsp;that the external memory is an LPDDR4-3200 16-bit wide (transfer rate of 3200 MT/s --&amp;gt; 1.6GHz I/O bus clock).&amp;nbsp;Taking into account that the external memory is DDR it means that the memory can handle 32-bits in one clock. Both AXI Bus and the A53 are 64-bit wide. However the frequency of the AXI bus is half (800MHz) of the frequency of the A53(1.5GHz).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If all of the above is correct, this architecture may lead to latency and performance issues. isn't it?&lt;/P&gt;&lt;P&gt;In addition, according to ARM documentation the The A53 L2 memory system interfaces to the external memory is 128-bits wide. how does it match to the fact the the AXI bus is 64-bits wide?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Nissim.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 11 Apr 2020 13:16:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087347#M159374</guid>
      <dc:creator>nissim</dc:creator>
      <dc:date>2020-04-11T13:16:46Z</dc:date>
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    <item>
      <title>Re: The relation between ARM Cortex A53 64-bit and LPDDR4 16-bit</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087348#M159375</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Internal details of i.MX8Mn are not provided. Nevertheless, because of internal DDRC buffer(s)&lt;/P&gt;&lt;P&gt;it is possible to avoid performance issues.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Apr 2020 09:39:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087348#M159375</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2020-04-14T09:39:01Z</dc:date>
    </item>
    <item>
      <title>Re: The relation between ARM Cortex A53 64-bit and LPDDR4 16-bit</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087349#M159376</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nissim,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is possible to achieve 3200MT/s using AXIS Bus.&lt;/P&gt;&lt;P&gt;Axis bus has 800MHz x 64bit = 51200 Mb/s&lt;/P&gt;&lt;P&gt;And LPDDR4 has 1600MHZ x 2 (DDR) x 16bit =&amp;nbsp;&lt;SPAN&gt;51200 Mb/s.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So there will not be any latency issue. If it is there then it can be handled by DDRC buffer as said by yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Mrudang&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Apr 2020 14:52:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/The-relation-between-ARM-Cortex-A53-64-bit-and-LPDDR4-16-bit/m-p/1087349#M159376</guid>
      <dc:creator>mrudangshelat1</dc:creator>
      <dc:date>2020-04-14T14:52:41Z</dc:date>
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