<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: ECSPI data tx/rx in LSB/MSB Control in iMX8MM in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI-data-tx-rx-in-LSB-MSB-Control-in-iMX8MM/m-p/1079441#M158399</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;Sreedhar&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are right,&amp;nbsp;ECSPI hardware does not support byte re-ordering.&lt;/P&gt;&lt;P&gt;One will have to implement it in software.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 22 Jul 2020 23:41:24 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2020-07-22T23:41:24Z</dc:date>
    <item>
      <title>ECSPI data tx/rx in LSB/MSB Control in iMX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI-data-tx-rx-in-LSB-MSB-Control-in-iMX8MM/m-p/1079440#M158398</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From the HW reference manual in iMX8MM of ECSPI&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;10.1.2.8 Byte Order&lt;/STRONG&gt;&lt;BR /&gt;The ECSPI does not support byte re-ordering in hardware.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there any method / procedure to setup ECSPI for LSB or MSB first transfer&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;Sreedhar&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 22 Jul 2020 20:29:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI-data-tx-rx-in-LSB-MSB-Control-in-iMX8MM/m-p/1079440#M158398</guid>
      <dc:creator>sreedhar_appala</dc:creator>
      <dc:date>2020-07-22T20:29:55Z</dc:date>
    </item>
    <item>
      <title>Re: ECSPI data tx/rx in LSB/MSB Control in iMX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI-data-tx-rx-in-LSB-MSB-Control-in-iMX8MM/m-p/1079441#M158399</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;Sreedhar&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are right,&amp;nbsp;ECSPI hardware does not support byte re-ordering.&lt;/P&gt;&lt;P&gt;One will have to implement it in software.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 22 Jul 2020 23:41:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI-data-tx-rx-in-LSB-MSB-Control-in-iMX8MM/m-p/1079441#M158399</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-07-22T23:41:24Z</dc:date>
    </item>
  </channel>
</rss>

