i.MX ProcessorsのトピックRe: Code Bus Cache and System Bus Cache

Code Bus Cache and System Bus Cache

anjalikkrishna — Wed, 22 Jul 2020 08:05:51 GMT

Hi All,

I am working on i.MX8 . The reference manual of the same talks about Code Bus Cache and system bus cache in multiple places. What exactly are they.? Are they cache for instruction code and data ? Then why are they called Code "Bus" Cache and system "Bus" cache?

Help would be appreciated.

Re: Code Bus Cache and System Bus Cache

Yuri — Wed, 22 Jul 2020 09:48:00 GMT

anjalikkrishna

Hello,

The terms Code Bus Cache and System Bus Cache concern the Cortex-M4 processor

(as part of i.MX8), which has "a modified 32-bit Harvard bus architecture. Using a 32-bit
address space, low-order addresses (0x0000_0000 through 0x1FFF_FFFF) use the
Processor Code (PC) bus, and high-order addresses (0x2000_0000 through
0xFFFF_FFFF) use the Processor System (PS) bus. As the bus names imply, normal
operation has code accesses on the PC bus and data accesses on the PS bus.

This device has been augmented with tightly-coupled memories for the PC and PS buses.
The memories include RAMs and caches. These local memories provide zero wait state
access to RAM and cacheable address spaces.

The local memory controller includes four memory controllers and their attached memories:
• SRAM lower (SRAM_L) controller via the PC bus
• SRAM upper (SRAM_U) controller via the PS bus
• Cache memory controller via the PC bus
• Cache memory controller via the PS bus"

Regards,

Yuri.

Re: Code Bus Cache and System Bus Cache

Zodiac — Wed, 23 Sep 2020 13:30:52 GMT

Hi anjalikkrishna,

Code Bus and System bus are ARMv7 memory system concepts, in which Code Bus covers 0x0000_0000 - 0x1FFF_FFFF, and System bus covers 0x2000_0000 - 0xFFFF_FFFF.

On iMX8 (M4 as an example) the cache controlled is implemented as LMEM (outer of processor), there are two cache parts, one mapped to Code Bus, the other mapped to System bus.

That's why they are called this way.

But both Code Bus Cache and System Bus cache can cache for instructions and data on its own mapped memory region.

This depends on the memory attributes on each memory region by default or configured by MPU.