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    <title>topic Re: Android 9 iMX8MM DDR4 Crash in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070681#M157285</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes one can try to tweak these parameters,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 28 Jul 2020 08:33:32 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2020-07-28T08:33:32Z</dc:date>
    <item>
      <title>Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070675#M157279</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;RAM is&amp;nbsp;MT40A512M16LY-075:E 2GB.&amp;nbsp; I used MX8M_Mini_DDR4_RPA_v11 with ddr_tool_v3.10 for calibration and it passes without issue.&amp;nbsp; I also ran an over-night test and had no problems.&amp;nbsp; In u-boot I'm seeing the following&amp;nbsp;&amp;lt;see below&amp;gt;&amp;nbsp;when training is run.&amp;nbsp; When compared to the evk the training points are different, the evk is&amp;nbsp;using 2400 1D, 400 1D, 100 1D, and 2400 2D.&amp;nbsp; Am I missing something when porting in the ddr4_timing.c from the&amp;nbsp;DDR tool to u-boot imx_v2018.03_4.14.98_2.1.0?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPL&amp;nbsp;PMIC&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;/* increase VDD_DRAM to 0.975v for 3Ghz DDR */&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#ifndef CONFIG_IMX8M_LPDDR4&lt;BR /&gt; /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);&lt;/P&gt;&lt;P&gt;#endif&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also&amp;nbsp;calibrated&amp;nbsp;with and without adjusting the PMIC from the ds file&lt;/P&gt;&lt;P&gt;sysparam set pmic_cfg 0x004b&lt;BR /&gt;sysparam set pmic_set 0x2f01 #REG_LOCK&lt;BR /&gt;sysparam set pmic_set 0x0d0f #BUCK1_VOLT_RUN 0.85v&lt;BR /&gt;sysparam set pmic_set 0x100f #BUCK2_VOLT_RUN 0.85v&lt;BR /&gt;sysparam set pmic_set 0x1483 #BUCK5_VOLT .975v&lt;BR /&gt;sysparam set pmic_set 0x1728 #BUCK8_VOLT 1.2v&lt;BR /&gt;sysparam set pmic_set 0x2f01 #REG_LOCK&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I did have to add&amp;nbsp;&lt;/P&gt;&lt;P&gt;busfreq {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;status = "disabled";&lt;BR /&gt; }&lt;/P&gt;&lt;P&gt;to the device tree otherwise, the system would freeze.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;U-Boot SPL 2018.03-dirty (Jul 06 2020 - 17:28:51 +0000)&lt;BR /&gt;power_bd71837_init&lt;BR /&gt;DDRINFO: start DRAM init&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DRAM PHY training for 1336MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training FAILED&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DDRINFO:ddrphy calibration done&lt;BR /&gt;DDRINFO: ddrmix config done&lt;BR /&gt;Normal Boot&lt;BR /&gt;Trying to boot from USB SDP&lt;BR /&gt;Index 0 1&lt;BR /&gt;board_usb_init&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;struct dram_fsp_msg ddr_dram_fsp_msg[] = {&lt;BR /&gt; {&lt;BR /&gt; /* P0 2400mts 1D */&lt;BR /&gt; .drate = 2400,&lt;BR /&gt; .fw_type = FW_1D_IMAGE,&lt;BR /&gt; .fsp_cfg = ddr_fsp0_cfg,&lt;BR /&gt; .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),&lt;BR /&gt; },&lt;BR /&gt; {&lt;BR /&gt; /* P1 1336mts 1D */&lt;BR /&gt; .drate = 1336,&lt;BR /&gt; .fw_type = FW_1D_IMAGE,&lt;BR /&gt; .fsp_cfg = ddr_fsp1_cfg,&lt;BR /&gt; .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),&lt;BR /&gt; },&lt;BR /&gt; {&lt;BR /&gt; /* P0 2400mts 2D */&lt;BR /&gt; .drate = 2400,&lt;BR /&gt; .fw_type = FW_2D_IMAGE,&lt;BR /&gt; .fsp_cfg = ddr_fsp0_2d_cfg,&lt;BR /&gt; .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),&lt;BR /&gt; },&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[ 9.091097] Internal error: undefined instruction: 0 [#1] PREEMPT SMP&lt;BR /&gt;[ 9.097580] Modules linked in: wlan(+)&lt;BR /&gt;[ 9.101348] CPU: 2 PID: 3101 Comm: ip6tables-resto Not tainted 4.14.98-dirty #6&lt;BR /&gt;[ 9.108659] Hardware name: DCI i.MX8MM CBX3G board (DT)&lt;BR /&gt;[ 9.113886] task: ffff800073761c00 task.stack: ffff000013f10000&lt;BR /&gt;[ 9.119815] PC is at update_curr+0x30/0x224&lt;BR /&gt;[ 9.124003] LR is at dequeue_task_fair+0x6c/0x1068&lt;BR /&gt;[ 9.128794] pc : [&amp;lt;ffff000008114090&amp;gt;] lr : [&amp;lt;ffff000008117234&amp;gt;] pstate: 200001c5&lt;BR /&gt;[ 9.136191] sp : ffff000013f13af0&lt;BR /&gt;[ 9.139506] x29: ffff000013f13af0 x28: ffff80007ff97870&lt;BR /&gt;[ 9.144821] x27: ffff80007ff97800 x26: ffff0000098f4000&lt;BR /&gt;[ 9.150135] x25: ffff800073762250 x24: ffff80007ff97800&lt;BR /&gt;[ 9.155449] x23: ffff0000098f2018 x22: 0000000000000001&lt;BR /&gt;[ 9.160763] x21: ffff80007ff97870 x20: ffff80007ff97800&lt;BR /&gt;[ 9.166076] x19: ffff800073761c80 x18: 0000ffffe572a3ba&lt;BR /&gt;[ 9.171390] x17: 0000e450eb474188 x16: ffff00000829ec28&lt;BR /&gt;[ 9.176703] x15: 0000000000000006 x14: 00000000ffffffff&lt;BR /&gt;[ 9.182018] x13: 0000e450eae27680 x12: 0000e450eae27380&lt;BR /&gt;[ 9.187332] x11: 0000000000000000 x10: 0000000000000000&lt;BR /&gt;[ 9.192646] x9 : 00000000ffffffff x8 : 000000000000003f&lt;BR /&gt;[ 9.197960] x7 : 0000000000000000 x6 : 000000003eefbbb3&lt;BR /&gt;[ 9.203274] x5 : 000000021b6c8d5c x4 : 0000000000000000&lt;BR /&gt;[ 9.208588] x3 : 00000000000001c0 x2 : 0000000000005a9d&lt;BR /&gt;[ 9.213902] x1 : ffff800073761c00 x0 : 000000021b71d27b&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Jul 2020 18:53:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070675#M157279</guid>
      <dc:creator>michaeldonahoe</dc:creator>
      <dc:date>2020-07-06T18:53:41Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070676#M157280</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Just an update.&amp;nbsp;&amp;nbsp;I corrected the BUCK2 to voltage to 1.0v, previously was 0.85v and the system now appears to be stable.&amp;nbsp; However, I still do receive a training FAIL for 1336.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;pmic_reg_write(p, BD71837_REGLOCK, 0x1);&lt;/P&gt;&lt;P&gt;/* increase VDD_SOC to typical value 0.85v before first DRAM access */&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); //0.85v&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x1E); //1.0v&lt;/P&gt;&lt;P&gt;/* increase VDD_DRAM to 0.975v for 3Ghz DDR */&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);&lt;/P&gt;&lt;P&gt;#ifndef CONFIG_IMX8M_LPDDR4&lt;BR /&gt; /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */&lt;BR /&gt; pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);&lt;BR /&gt;#endif&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Jul 2020 03:24:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070676#M157280</guid>
      <dc:creator>michaeldonahoe</dc:creator>
      <dc:date>2020-07-07T03:24:59Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070677#M157281</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Michael&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; When compared to the evk the training points are different, the evk&lt;/P&gt;&lt;P&gt;&amp;gt;is&amp;nbsp;using 2400 1D, 400 1D, 100 1D, and 2400 2D.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this is described in MX8M_Mini_DDR4_RPA_v11.xlsx Revision History&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/114905i5AAA002EF72977DD/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.jpg" alt="pastedImage_1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For training fail one can try to follow sect.4.3 Building u-boot image&lt;/P&gt;&lt;P&gt;MSCALE_DDR_Tool_User_Guide.pdf included in &lt;A _jive_internal="true" data-content-finding="Community" href="https://community.nxp.com/servlet/JiveServlet/download/340179-63-464954/mscale_ddr_tool_v310_setup.exe.zip"&gt;mscale_ddr_tool_v310_setup.exe.zip&lt;/A&gt;&lt;/P&gt;&lt;P&gt;sect.4.3.1 Building u-boot image by toolchain command..&lt;/P&gt;&lt;P&gt;Step3b. Replace DDR4 firmware and copy u-boot to imx_mkimage directory&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Jul 2020 00:35:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070677#M157281</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-07-08T00:35:32Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070678#M157282</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Igor.&amp;nbsp; Unfortunately, I did replace the training binaries and copied the u-boot bins.&amp;nbsp; I repeated the whole process just to confirm I did not miss anything, but I still have a training error.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;625b90ed492425bec9c7fced37671c233a12d7bea9e050b72b2d62c8e7713aa5 iMX8M/ddr4_dmem_1d.bin&lt;BR /&gt;4cd3cd4340cc4aade5c1bacda3c6044b257838e543e613d93d6480317c3ad514 iMX8M/ddr4_dmem_2d.bin&lt;BR /&gt;6d65841d78bdd2d99df17e14fa4674b52111149d2161888e3c24527ac86d9591 iMX8M/ddr4_imem_1d.bin&lt;BR /&gt;3e24c256ec170f39bd85a7ab60dadb1ea47502dc272825a13135a1b5575ed5a3 iMX8M/ddr4_imem_2d.bin&lt;BR /&gt;1ee3ef869a748e7f11d36e359a8f1a773658d23ff74b841d97a3ac11c840a120 iMX8M/ddr4_train1d_string.bin&lt;BR /&gt;10a7bd10b76eb8efcb3994bcbd3a6b4032f8fb9b52ca2f4310128908c9382671 iMX8M/ddr4_train2d_string.bin&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;FIT description: Configuration to load ATF before U-Boot&lt;BR /&gt;Created: Fri Jul 10 13:10:49 2020&lt;BR /&gt; Image 0 (uboot@1)&lt;BR /&gt; Description: U-Boot (64-bit)&lt;BR /&gt; Created: Fri Jul 10 13:10:49 2020&lt;BR /&gt; Type: Standalone Program&lt;BR /&gt; Compression: uncompressed&lt;BR /&gt; Data Size: unavailable&lt;BR /&gt; Architecture: AArch64&lt;BR /&gt; Load Address: 0x40200000&lt;BR /&gt; Entry Point: unavailable&lt;BR /&gt; Image 1 (atf@1)&lt;BR /&gt; Description: ARM Trusted Firmware&lt;BR /&gt; Created: Fri Jul 10 13:10:49 2020&lt;BR /&gt; Type: Firmware&lt;BR /&gt; Compression: uncompressed&lt;BR /&gt; Data Size: unavailable&lt;BR /&gt; Architecture: AArch64&lt;BR /&gt; Load Address: 0x00920000&lt;BR /&gt; Image 2 (fdt@1)&lt;BR /&gt; Description: fsl-imx8mm-ddr4-val&lt;BR /&gt; Created: Fri Jul 10 13:10:49 2020&lt;BR /&gt; Type: Flat Device Tree&lt;BR /&gt; Compression: uncompressed&lt;BR /&gt; Data Size: unavailable&lt;/P&gt;&lt;P&gt;Compression: uncompressed [44/1793]&lt;BR /&gt; Data Size: unavailable&lt;BR /&gt; Architecture: Unknown Architecture&lt;BR /&gt; Default Configuration: 'config@1'&lt;BR /&gt; Configuration 0 (config@1)&lt;BR /&gt; Description: fsl-imx8mm-ddr4-val&lt;BR /&gt; Kernel: unavailable&lt;BR /&gt; FDT: fdt@1&lt;BR /&gt; Loadables: atf@1&lt;BR /&gt;./mkimage_imx8 -version v1 -fit -loader u-boot-spl-ddr4.bin 0x7E1000 -second_loader u-boot-ddr4.itb 0x40400000 0x60000 -out flash.bin&lt;BR /&gt;Platform: i.MX8M (mScale)&lt;BR /&gt;ROM VERSION: v1&lt;BR /&gt;Using FIT image&lt;BR /&gt;LOADER IMAGE: u-boot-spl-ddr4.bin start addr: 0x007e1000&lt;BR /&gt;SECOND LOADER IMAGE: u-boot-ddr4.itb start addr: 0x40400000 offset: 0x00060000&lt;BR /&gt;Output: flash.bin&lt;BR /&gt;========= IVT HEADER [HDMI FW] =========&lt;BR /&gt;header.tag: 0x0&lt;BR /&gt;header.length: 0x0&lt;BR /&gt;header.version: 0x0&lt;BR /&gt;entry: 0x0&lt;BR /&gt;reserved1: 0x0&lt;BR /&gt;dcd_ptr: 0x0&lt;BR /&gt;boot_data_ptr: 0x0&lt;BR /&gt;self: 0x0&lt;BR /&gt;csf: 0x0&lt;BR /&gt;reserved2: 0x0&lt;BR /&gt;boot_data.start: 0x0&lt;BR /&gt;boot_data.size: 0x0&lt;BR /&gt;boot_data.plugin: 0x0&lt;BR /&gt;========= IVT HEADER [PLUGIN] =========&lt;BR /&gt;header.tag: 0x0&lt;BR /&gt;header.length: 0x0&lt;BR /&gt;header.version: 0x0&lt;BR /&gt;entry: 0x0&lt;BR /&gt;reserved1: 0x0&lt;BR /&gt;dcd_ptr: 0x0&lt;BR /&gt;boot_data_ptr: 0x0&lt;/P&gt;&lt;P&gt;dcd_ptr: 0x0 [8/1793]&lt;BR /&gt;boot_data_ptr: 0x0&lt;BR /&gt;self: 0x0&lt;BR /&gt;csf: 0x0&lt;BR /&gt;reserved2: 0x0&lt;BR /&gt;boot_data.start: 0x0&lt;BR /&gt;boot_data.size: 0x0&lt;BR /&gt;boot_data.plugin: 0x0&lt;BR /&gt;========= IVT HEADER [LOADER IMAGE] =========&lt;BR /&gt;header.tag: 0xd1&lt;BR /&gt;header.length: 0x2000&lt;BR /&gt;header.version: 0x41&lt;BR /&gt;entry: 0x7e1000&lt;BR /&gt;reserved1: 0x57c00&lt;BR /&gt;dcd_ptr: 0x0&lt;BR /&gt;boot_data_ptr: 0x7e0fe0&lt;BR /&gt;self: 0x7e0fc0&lt;BR /&gt;csf: 0x80a5c0&lt;BR /&gt;reserved2: 0x0&lt;BR /&gt;boot_data.start: 0x7e0bc0&lt;BR /&gt;boot_data.size: 0x2ba00&lt;BR /&gt;boot_data.plugin: 0x0&lt;BR /&gt;========= OFFSET dump =========&lt;BR /&gt;Loader IMAGE:&lt;BR /&gt; header_image_off 0x0&lt;BR /&gt; dcd_off 0x0&lt;BR /&gt; image_off 0x40&lt;BR /&gt; csf_off 0x29600&lt;BR /&gt; spl hab block: 0x7e0fc0 0x0 0x29600&lt;/P&gt;&lt;P&gt;Second Loader IMAGE:&lt;BR /&gt; sld_header_off 0x57c00&lt;BR /&gt; sld_csf_off 0x58c20&lt;BR /&gt; sld hab block: 0x403fcdc0 0x57c00 0x1020&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;U-Boot SPL 2018.03-01210-gbfafde0-dirty (Jul 10 2020 - 13:10:31 -0500)&lt;BR /&gt;power_bd71837_init&lt;BR /&gt;DDRINFO: start DRAM init&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DRAM PHY training for 1336MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training FAILED&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DDRINFO:ddrphy calibration done&lt;BR /&gt;DDRINFO: ddrmix config done&lt;BR /&gt;Normal Boot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I calibrated and updated using 533 and then everything passed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;U-Boot SPL 2018.03-01210-gbfafde0-dirty (Jul 10 2020 - 13:57:00 -0500)&lt;BR /&gt;power_bd71837_init&lt;BR /&gt;DDRINFO: start DRAM init&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DRAM PHY training for 1066MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DRAM PHY training for 2400MTS&lt;BR /&gt;check ddr_pmu_train_imem code&lt;BR /&gt;check ddr_pmu_train_imem code pass&lt;BR /&gt;check ddr_pmu_train_dmem code&lt;BR /&gt;check ddr_pmu_train_dmem code pass&lt;BR /&gt;Training PASS&lt;BR /&gt;DDRINFO:ddrphy calibration done&lt;BR /&gt;DDRINFO: ddrmix config done&lt;BR /&gt;Normal Boot&lt;BR /&gt;Trying to boot from USB SDP&lt;BR /&gt;Index 0 1&lt;BR /&gt;board_usb_init&lt;BR /&gt;USB OTG Index 0&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jul 2020 18:59:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070678#M157282</guid>
      <dc:creator>michaeldonahoe</dc:creator>
      <dc:date>2020-07-10T18:59:37Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070679#M157283</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Michael&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;currently officially supported 2400/1066 i.MXM Mini ddr4 setpoints as in your tests.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regarding 1336 - it is not supported for i.MXM Mini ddr4, I sent you additional material via mail.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In general one can tweak drive strength and ODT parameters in RPA tool.&lt;/P&gt;&lt;P&gt;Also may be recommended to try more new uboot releases as&lt;/P&gt;&lt;P&gt;imx_v2018.03_4.14.98_2.1.0 is very old.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 11 Jul 2020 05:46:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070679#M157283</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-07-11T05:46:06Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070680#M157284</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the RPA excel file for the drive strength and ODT parameter, are only&amp;nbsp;ATxImpedance, ODTImpedance and&amp;nbsp;TxImpedance and modify?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Or other parameters can modify?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Chris Lin&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Jul 2020 07:15:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070680#M157284</guid>
      <dc:creator>chrislin_wpi</dc:creator>
      <dc:date>2020-07-28T07:15:49Z</dc:date>
    </item>
    <item>
      <title>Re: Android 9 iMX8MM DDR4 Crash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070681#M157285</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes one can try to tweak these parameters,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Jul 2020 08:33:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Android-9-iMX8MM-DDR4-Crash/m-p/1070681#M157285</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-07-28T08:33:32Z</dc:date>
    </item>
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