IMX6 run mode LDO enabled /LDO bypassed switch

864535720 — Mon, 11 May 2020 07:56:21 GMT

Hello everyone,
In the process of using imx6d self-made development board, we set the run mode to LDO enabled mode. After the kernel starts, we go to measure the voltage of VDD_ARM_IN and find that at a frequency of 996MHz, the voltage is 1.25V. According to the manual, in 996MHz, LDO mode, the voltage of VDD_ARM_IN should be 1.35V (min) -1.5V (max). How can I correct this voltage?

Re: IMX6 run mode LDO enabled /LDO bypassed switch

Yuri — Mon, 11 May 2020 08:19:03 GMT

Hello,

Use DTS file to configure voltages.

https://community.nxp.com/message/953900

Regards,

Yuri.

Re: IMX6 run mode LDO enabled /LDO bypassed switch

864535720 — Mon, 11 May 2020 08:32:05 GMT

My dts information is as follows：

cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS_SRC> ;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};

If my run mode is set to LDO enabled mode, should it be modified as follows:

cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1400000
996000 1350000
852000 1275000
792000 1275000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1400000
996000 1350000
852000 1275000
792000 1275000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS_SRC> ;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};

Will I have any problems with this modification?

i.MX ProcessorsのトピックRe: IMX6 run mode LDO enabled /LDO bypassed switch

IMX6 run mode LDO enabled /LDO bypassed switch

Re: IMX6 run mode LDO enabled /LDO bypassed switch

Re: IMX6 run mode LDO enabled /LDO bypassed switch