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    <title>i.MX Processorsのトピックi.MX6Q arm_dcache_invalidate() bug?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224724#M15662</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;According to "&lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;ARM&lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;® &lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;Architecture Reference Manual &lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;ARMv7-A and ARMv7-R edition", section "&lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;B4.1.19 &lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;CCSIDR, Cache Size ID Registers, VMSA", NumSets is in bits 13-27.&amp;nbsp; The source code that is shipped with the i.MX6Q Platform SDK uses 0x13 not 13.&amp;nbsp; Is this a bug or am I missing something?&amp;nbsp; The Freescale code is listed below&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;Andrew.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV class="column"&gt; &lt;/DIV&gt;&lt;P&gt;&lt;SPAN style="color: #0433ff;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&lt;SPAN style="color: #0433ff;"&gt;void&lt;/SPAN&gt; arm_dcache_invalidate()&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;{&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; uint32_t csid;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// Cache Size ID&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; uint32_t wayset;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// wayset parameter &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #0433ff;"&gt;int&lt;/SPAN&gt;&lt;SPAN style="color: #000000;"&gt; num_sets; &lt;/SPAN&gt;// number of sets&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #0433ff;"&gt;int&lt;/SPAN&gt;&lt;SPAN style="color: #000000;"&gt; num_ways; &lt;/SPAN&gt;// number of ways&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_MRC(15, 1, csid, 0, 0, 0);&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// Read Cache Size ID &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// Fill number of sets&amp;nbsp; and number of ways from csid register&amp;nbsp; This walues are decremented by 1&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_ways = (csid &amp;gt;&amp;gt; 0x03) &amp;amp; 0x3FFu; &lt;/SPAN&gt;//((csid&amp;amp; csid_ASSOCIATIVITY_MASK) &amp;gt;&amp;gt; csid_ASSOCIATIVITY_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// Invalidation all lines (all Sets in all ways) &lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #0433ff;"&gt;while&lt;/SPAN&gt; (num_ways &amp;gt;= 0)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_sets = (csid &amp;gt;&amp;gt; 0x13) &amp;amp; 0x7FFFu; &lt;/SPAN&gt;//((csid &amp;amp; csid_NUMSETS_MASK) &amp;gt;&amp;gt; csid_NUMSETS_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #0433ff;"&gt;while&lt;/SPAN&gt; (num_sets &amp;gt;= 0 )&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; wayset = (num_sets &amp;lt;&amp;lt; 5u) | (num_ways &amp;lt;&amp;lt; 30u); &lt;/SPAN&gt;//(num_sets &amp;lt;&amp;lt; SETWAY_SET_SHIFT) | (num_sets &amp;lt;&amp;lt; 3SETWAY_WAY_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// invalidate line if we know set and way &lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_MCR(15, 0, wayset, 7, 6, 2);&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_sets--;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_ways--;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_DSB();&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;}&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Sep 2013 02:36:24 GMT</pubDate>
    <dc:creator>andrewtrotman</dc:creator>
    <dc:date>2013-09-11T02:36:24Z</dc:date>
    <item>
      <title>i.MX6Q arm_dcache_invalidate() bug?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224724#M15662</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;According to "&lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;ARM&lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;® &lt;/SPAN&gt;&lt;SPAN style="font-family: ArialMT;"&gt;Architecture Reference Manual &lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;ARMv7-A and ARMv7-R edition", section "&lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;B4.1.19 &lt;/SPAN&gt;&lt;SPAN style="font-family: Arial;"&gt;CCSIDR, Cache Size ID Registers, VMSA", NumSets is in bits 13-27.&amp;nbsp; The source code that is shipped with the i.MX6Q Platform SDK uses 0x13 not 13.&amp;nbsp; Is this a bug or am I missing something?&amp;nbsp; The Freescale code is listed below&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;Andrew.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Arial;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV class="column"&gt; &lt;/DIV&gt;&lt;P&gt;&lt;SPAN style="color: #0433ff;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&lt;SPAN style="color: #0433ff;"&gt;void&lt;/SPAN&gt; arm_dcache_invalidate()&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;{&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; uint32_t csid;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// Cache Size ID&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; uint32_t wayset;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// wayset parameter &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #0433ff;"&gt;int&lt;/SPAN&gt;&lt;SPAN style="color: #000000;"&gt; num_sets; &lt;/SPAN&gt;// number of sets&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #0433ff;"&gt;int&lt;/SPAN&gt;&lt;SPAN style="color: #000000;"&gt; num_ways; &lt;/SPAN&gt;// number of ways&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_MRC(15, 1, csid, 0, 0, 0);&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #008f00;"&gt;// Read Cache Size ID &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// Fill number of sets&amp;nbsp; and number of ways from csid register&amp;nbsp; This walues are decremented by 1&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_ways = (csid &amp;gt;&amp;gt; 0x03) &amp;amp; 0x3FFu; &lt;/SPAN&gt;//((csid&amp;amp; csid_ASSOCIATIVITY_MASK) &amp;gt;&amp;gt; csid_ASSOCIATIVITY_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// Invalidation all lines (all Sets in all ways) &lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #0433ff;"&gt;while&lt;/SPAN&gt; (num_ways &amp;gt;= 0)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_sets = (csid &amp;gt;&amp;gt; 0x13) &amp;amp; 0x7FFFu; &lt;/SPAN&gt;//((csid &amp;amp; csid_NUMSETS_MASK) &amp;gt;&amp;gt; csid_NUMSETS_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #0433ff;"&gt;while&lt;/SPAN&gt; (num_sets &amp;gt;= 0 )&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; wayset = (num_sets &amp;lt;&amp;lt; 5u) | (num_ways &amp;lt;&amp;lt; 30u); &lt;/SPAN&gt;//(num_sets &amp;lt;&amp;lt; SETWAY_SET_SHIFT) | (num_sets &amp;lt;&amp;lt; 3SETWAY_WAY_SHIFT)&lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// invalidate line if we know set and way &lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_MCR(15, 0, wayset, 7, 6, 2);&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_sets--;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num_ways--;&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: Menlo; color: #008f00;"&gt;&lt;SPAN style="color: #000000;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _ARM_DSB();&lt;/P&gt;&lt;P style="font-family: Menlo;"&gt;}&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 02:36:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224724#M15662</guid>
      <dc:creator>andrewtrotman</dc:creator>
      <dc:date>2013-09-11T02:36:24Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6Q arm_dcache_invalidate() bug?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224725#M15663</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Nice catch, Andrew. Yes, it is a bug which was fixed in SDK_RELEASE_V1.1. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 05:20:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224725#M15663</guid>
      <dc:creator>JerryFan</dc:creator>
      <dc:date>2013-09-11T05:20:34Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6Q arm_dcache_invalidate() bug?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224726#M15664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;Thanks for the confirmation. I've noticed that the same bug also appears in arm_dcache_flush(). Is it fixed there too?&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 07:46:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224726#M15664</guid>
      <dc:creator>andrewtrotman</dc:creator>
      <dc:date>2013-09-11T07:46:30Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6Q arm_dcache_invalidate() bug?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224727#M15665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, the bug in arm_dcache_flush had also been fixed.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 07:49:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224727#M15665</guid>
      <dc:creator>JerryFan</dc:creator>
      <dc:date>2013-09-11T07:49:45Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6Q arm_dcache_invalidate() bug?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224728#M15666</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;Thanks. I'll update to the new version. &lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 08:15:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6Q-arm-dcache-invalidate-bug/m-p/224728#M15666</guid>
      <dc:creator>andrewtrotman</dc:creator>
      <dc:date>2013-09-11T08:15:12Z</dc:date>
    </item>
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