<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックiMX8 Nano DDR4 DRAM_VREF capacitor values</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064975#M156518</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Looking at the NXP reference design for the iMX8 Nano with DDR4, there are some 1uF and 0.01uF capacitors used to filter the generated DRAM_VREF signal.&amp;nbsp; Are these capacitor values critical? Specifically, is there any problem with using 4.7uF in those 3 locations? (Because we already have a bunch of 4.7uF's on the board, so I'd like to limit the number of BOM items - particularly that 0.01uF as it's the only one on the board.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/106710iD4F992FD93FDB7C4/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 09 May 2020 00:36:55 GMT</pubDate>
    <dc:creator>frank_vanhooft</dc:creator>
    <dc:date>2020-05-09T00:36:55Z</dc:date>
    <item>
      <title>iMX8 Nano DDR4 DRAM_VREF capacitor values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064975#M156518</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Looking at the NXP reference design for the iMX8 Nano with DDR4, there are some 1uF and 0.01uF capacitors used to filter the generated DRAM_VREF signal.&amp;nbsp; Are these capacitor values critical? Specifically, is there any problem with using 4.7uF in those 3 locations? (Because we already have a bunch of 4.7uF's on the board, so I'd like to limit the number of BOM items - particularly that 0.01uF as it's the only one on the board.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/106710iD4F992FD93FDB7C4/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 May 2020 00:36:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064975#M156518</guid>
      <dc:creator>frank_vanhooft</dc:creator>
      <dc:date>2020-05-09T00:36:55Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8 Nano DDR4 DRAM_VREF capacitor values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064976#M156519</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am confirming it and give you reply as soon as possible.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 May 2020 05:55:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064976#M156519</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2020-05-09T05:55:09Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8 Nano DDR4 DRAM_VREF capacitor values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064977#M156520</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; The C389 and C390 can change to 4.7uF from 1uF, please note the value of the two capacitor must be the same, But C110 can not be changed, C110&amp;nbsp;and C389 are in parallel.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 May 2020 06:54:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-Nano-DDR4-DRAM-VREF-capacitor-values/m-p/1064977#M156520</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2020-05-09T06:54:20Z</dc:date>
    </item>
  </channel>
</rss>

