i.MX ProcessorsのトピックMore than 4 CS lines for SPI https://community.nxp.com/t5/i-MX-Processors/More-than-4-CS-lines-for-SPI/m-p/1064886#M156502 <HTML><HEAD></HEAD><BODY><P>The documentation&nbsp;for iMX6UL and iMX8 says SPI has 4 CS lines.</P><P><BR />I intend to&nbsp;use a total of 12 SPI devices connected to SPI1, 2 and 3 (4 in each).<BR />As far as I understood, I can configure CS pins as GPIO and use the kernel driver configurations to define all 12 CS lines from GPIOs.</P><P></P><P>Is my understanding correct or is there some hardware limitation I'm missing?</P><P></P><P>Thanks</P></BODY></HTML> Sat, 23 May 2020 03:57:47 GMT marcus_cps 2020-05-23T03:57:47Z More than 4 CS lines for SPI https://community.nxp.com/t5/i-MX-Processors/More-than-4-CS-lines-for-SPI/m-p/1064886#M156502 <HTML><HEAD></HEAD><BODY><P>The documentation&nbsp;for iMX6UL and iMX8 says SPI has 4 CS lines.</P><P><BR />I intend to&nbsp;use a total of 12 SPI devices connected to SPI1, 2 and 3 (4 in each).<BR />As far as I understood, I can configure CS pins as GPIO and use the kernel driver configurations to define all 12 CS lines from GPIOs.</P><P></P><P>Is my understanding correct or is there some hardware limitation I'm missing?</P><P></P><P>Thanks</P></BODY></HTML> Sat, 23 May 2020 03:57:47 GMT https://community.nxp.com/t5/i-MX-Processors/More-than-4-CS-lines-for-SPI/m-p/1064886#M156502 marcus_cps 2020-05-23T03:57:47Z Re: More than 4 CS lines for SPI https://community.nxp.com/t5/i-MX-Processors/More-than-4-CS-lines-for-SPI/m-p/1064887#M156503 <HTML><HEAD></HEAD><BODY><P>Hi Marcus</P><P></P><P>yes this understanding is correct.</P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Sun, 24 May 2020 23:21:04 GMT https://community.nxp.com/t5/i-MX-Processors/More-than-4-CS-lines-for-SPI/m-p/1064887#M156503 igorpadykov 2020-05-24T23:21:04Z