DDR Controller data abort recovery?

johnballance — Tue, 22 Oct 2013 18:10:39 GMT

is there anything I need to do with the DDR controller after it has caused a data abort through accessing non existent addresses? It seems happy on writes, but seems to give a data abort on reads.

Thanks

John

Re: DDR Controller data abort recovery?

Yuri — Mon, 28 Oct 2013 09:15:07 GMT

According to the i.MX6 Reference Manual :

“The following registers in the MMDC define the DDR address space:

• MDMISC[DDR_4_BANK]—Defines either 4 or 8 banks in the DDR device

• MDCTL[DSIZ]—Defines the DDR data bus width of x16, x32 or x64

• MDMISC[BI]—Defines whether bank interleaving is on or off

• MDCTL[COL]—Defines the column size of the DDR device

• MDCTL[ROW]—Defines the row size of the DDR device”.

Also, “It is optional to configure the partition between the chip selects through

MDASP[CS0_END]”.

Generally for an access to an address, which is not used (non-covered) by internal
i.MX6 modules, we can expect ARM data abort exception, but the following

statement (NOTE) may be considered as recommendation to avoid such accesses :

“In cases where this is an access to a non-initialized or disconnected chip select,

behavior may be unexpected”.

If it is required to define memory size – it makes sense to test it without checking

addresses, that are out of range. It is enough to test (quite accessible) memory region

via writing and consequent reading data, assuming they are equal for real memory.

topic Re: DDR Controller data abort recovery? in i.MX Processors

DDR Controller data abort recovery?

Re: DDR Controller data abort recovery?