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    <title>topic Re: IMX8QXP Kernel not working from LPUART1 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057876#M155556</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hallo Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the reply. According to your answer in the thread&amp;nbsp;&lt;A href="https://community.nxp.com/thread/493688"&gt;chaning the Debug port i.MX8QXP&lt;/A&gt;&amp;nbsp;, my u-boot has been configured exactly in same way. My u-boot lpuart1 is working. You can also check the unimog_imx8qxp.c file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;‌ as mentioned by you in the thread,&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Then you'll need to make similar changes in the U-Boot device tree: arch/arm/dts/fsl-imx8qxp*.dts*. MUX and clocks should be configured, though you might need to enable (&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;status = "okay";&lt;/EM&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;) lpuart3. Don't forget to include&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;CONFIG_FSL_LPUART=y&lt;/EM&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in your defconfig file.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The SOC device tree file provided from NXP uses pd_dma2_chan11 which is only the tx line dma. I have changed it to "&lt;STRONG&gt;pd_dma_lpuart1&lt;/STRONG&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;lpuart1: serial@5a070000 {&lt;BR /&gt; compatible = "fsl,imx8qm-lpuart";&lt;BR /&gt; reg = &amp;lt;0x0 0x5a070000 0x0 0x1000&amp;gt;;&lt;BR /&gt; interrupts = &amp;lt;GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt; interrupt-parent = &amp;lt;&amp;amp;wu&amp;gt;;&lt;BR /&gt; clocks = &amp;lt;&amp;amp;clk IMX8QXP_UART1_CLK&amp;gt;,&lt;BR /&gt; &amp;lt;&amp;amp;clk IMX8QXP_UART1_IPG_CLK&amp;gt;;&lt;BR /&gt; clock-names = "per", "ipg";&lt;BR /&gt; assigned-clocks = &amp;lt;&amp;amp;clk IMX8QXP_UART1_CLK&amp;gt;;&lt;BR /&gt; assigned-clock-rates = &amp;lt;80000000&amp;gt;;&lt;BR /&gt; power-domains = &amp;lt;&amp;amp;pd_dma2_chan11&amp;gt;;&lt;BR /&gt; dma-names = "tx","rx";&lt;BR /&gt; dmas = &amp;lt;&amp;amp;edma2 11 0 0&amp;gt;,&lt;BR /&gt; &amp;lt;&amp;amp;edma2 10 0 1&amp;gt;;&lt;BR /&gt; status = "disabled";&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;## My Device Tree ## in U-boot&lt;/P&gt;&lt;P&gt;pinctrl_lpuart1: lpuart1grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; SC_P_UART1_RX_ADMA_UART1_RX 0x06000020&lt;BR /&gt; SC_P_UART1_TX_ADMA_UART1_TX 0x06000020&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;lpuart1 {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_lpuart1&amp;gt;;&lt;BR /&gt; status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After correcting the LPUART1 dma from the device tree file. Now the Kernel is working.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 08 May 2020 01:43:06 GMT</pubDate>
    <dc:creator>mdmosaddekhossa</dc:creator>
    <dc:date>2020-05-08T01:43:06Z</dc:date>
    <item>
      <title>IMX8QXP Kernel not working from LPUART1</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057874#M155554</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;STRONG&gt;Hello NXP Team,&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Currently we are facing issue to boot the kernel in our iMX8QXP custom board. Via fastboot we are flashing the linux kernel and device tree from u-boot. When we try to boot the kernel no response is coming from the LPUART1. We are using LPUART1 instead of LPUART0 from reference MEK board.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Kernel version:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;4.19.35_1.1.0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Kernel Device Tree Using LPUART1:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;chosen {&lt;BR /&gt; bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";&lt;BR /&gt; stdout-path = &amp;amp;lpuart1;&lt;BR /&gt; };&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;iomuxc {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_hog&amp;gt;;&lt;/P&gt;&lt;P&gt;imx8qxp-sthu {&lt;/P&gt;&lt;P&gt;pinctrl_hog: hoggrp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;pinctrl_lpuart1: lpuart1grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; SC_P_UART1_RX_ADMA_UART1_RX 0x06000020&lt;BR /&gt; SC_P_UART1_TX_ADMA_UART1_TX 0x06000020&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;pd_dma_lpuart1 {&lt;BR /&gt; debug_console;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&amp;amp;lpuart1 {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_lpuart1&amp;gt;;&lt;BR /&gt; status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Defconfig:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Check the attachment.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Problem:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #f4f5f7; color: #172b4d; font-weight: 400; "&gt;These `/dma-controller@5a1f0000, 48852` messages come from u-boot. And `u-boot` successfully transfers control to linux.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="background-color: #f4f5f7; color: #172b4d; font-weight: 400; "&gt;But nothing comes out from Kernel lpuart1.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="kernel.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/61861iF307C23D95624BB4/image-size/large?v=v2&amp;amp;px=999" role="button" title="kernel.png" alt="kernel.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 May 2020 12:58:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057874#M155554</guid>
      <dc:creator>mdmosaddekhossa</dc:creator>
      <dc:date>2020-05-07T12:58:38Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8QXP Kernel not working from LPUART1</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057875#M155555</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Mosaddek&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can look at&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/493688"&gt;https://community.nxp.com/thread/493688&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 May 2020 23:41:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057875#M155555</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-05-07T23:41:38Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8QXP Kernel not working from LPUART1</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057876#M155556</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hallo Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the reply. According to your answer in the thread&amp;nbsp;&lt;A href="https://community.nxp.com/thread/493688"&gt;chaning the Debug port i.MX8QXP&lt;/A&gt;&amp;nbsp;, my u-boot has been configured exactly in same way. My u-boot lpuart1 is working. You can also check the unimog_imx8qxp.c file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;‌ as mentioned by you in the thread,&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Then you'll need to make similar changes in the U-Boot device tree: arch/arm/dts/fsl-imx8qxp*.dts*. MUX and clocks should be configured, though you might need to enable (&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;status = "okay";&lt;/EM&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;) lpuart3. Don't forget to include&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;CONFIG_FSL_LPUART=y&lt;/EM&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in your defconfig file.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The SOC device tree file provided from NXP uses pd_dma2_chan11 which is only the tx line dma. I have changed it to "&lt;STRONG&gt;pd_dma_lpuart1&lt;/STRONG&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;lpuart1: serial@5a070000 {&lt;BR /&gt; compatible = "fsl,imx8qm-lpuart";&lt;BR /&gt; reg = &amp;lt;0x0 0x5a070000 0x0 0x1000&amp;gt;;&lt;BR /&gt; interrupts = &amp;lt;GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt; interrupt-parent = &amp;lt;&amp;amp;wu&amp;gt;;&lt;BR /&gt; clocks = &amp;lt;&amp;amp;clk IMX8QXP_UART1_CLK&amp;gt;,&lt;BR /&gt; &amp;lt;&amp;amp;clk IMX8QXP_UART1_IPG_CLK&amp;gt;;&lt;BR /&gt; clock-names = "per", "ipg";&lt;BR /&gt; assigned-clocks = &amp;lt;&amp;amp;clk IMX8QXP_UART1_CLK&amp;gt;;&lt;BR /&gt; assigned-clock-rates = &amp;lt;80000000&amp;gt;;&lt;BR /&gt; power-domains = &amp;lt;&amp;amp;pd_dma2_chan11&amp;gt;;&lt;BR /&gt; dma-names = "tx","rx";&lt;BR /&gt; dmas = &amp;lt;&amp;amp;edma2 11 0 0&amp;gt;,&lt;BR /&gt; &amp;lt;&amp;amp;edma2 10 0 1&amp;gt;;&lt;BR /&gt; status = "disabled";&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;## My Device Tree ## in U-boot&lt;/P&gt;&lt;P&gt;pinctrl_lpuart1: lpuart1grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; SC_P_UART1_RX_ADMA_UART1_RX 0x06000020&lt;BR /&gt; SC_P_UART1_TX_ADMA_UART1_TX 0x06000020&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;lpuart1 {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_lpuart1&amp;gt;;&lt;BR /&gt; status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After correcting the LPUART1 dma from the device tree file. Now the Kernel is working.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 May 2020 01:43:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-Kernel-not-working-from-LPUART1/m-p/1057876#M155556</guid>
      <dc:creator>mdmosaddekhossa</dc:creator>
      <dc:date>2020-05-08T01:43:06Z</dc:date>
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