topic 8MQ for DDR4 in i.MX Processors

8MQ for DDR4

haochengdong — Wed, 20 May 2020 10:19:28 GMT

Why does the 8MQ DDR4 reference design use T PCB routing topology for a 2-rank system? Is it because the addressable range of a single DRAM_nCS is too small? Can it be designed as T PCB routing topology for a 1-rank system. Only one DRAM_nCS0 is used.

Re: 8MQ for DDR4

mrudangshelat1 — Tue, 26 May 2020 06:54:09 GMT

Hi,

It is possible to design 8MQ DDR4 PCB routing topology for a 1-rank system as long as you are able to get your requires memory density. The reference design has used 2 rank system to achieve their memory density.

Mrudang

Re: 8MQ for DDR4

gusarambula — Wed, 27 May 2020 01:49:42 GMT

Hello Haochengdong Haochengdong,

A 2-rank system is implemented on the EVK and recommended as it may provide better performance and it allows to use the T topology to mirror the chips and make it easier to design, although a single rank design is also possible, as Mrudang mentions.

However, in general terms I would recommend that you follow the recommendations for DDR design on the i.MX8QM Hardware Design Guide (link below, please note that you may need to login to download this document) unless you are very confident in DDR4 design as routing DDR4 memories can be challenging.

https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQHDG

I hope this helps!

Regards,