topic Re: iMX8M mini DDR Board Data Bus Configuration in RPA tool (MX8M_Mini_LPDDR4_RPA_v15.xlsx) in i.MX Processors

iMX8M mini DDR Board Data Bus Configuration in RPA tool (MX8M_Mini_LPDDR4_RPA_v15.xlsx)

girishprasadgm — Tue, 30 Jun 2020 14:08:38 GMT

I am trying to understand the DDR configuration for iMX8M mini, since soon i will be working on custom board based on iMX8M mini.

I am trying to configure the "BoardDataBusConfig" in "MX8M_Mini_LPDDR4_RPA_v15.xlsx". As per iMX8M mini evk schematic Lane A & B are swapped.

And the original "BoardDataBusConfig" has the below configuration

I have changed this configuration as shown below

With both original configuration and modified configuration DDR calibration is PASSED. Please help me in understanding what is differences between the above configuration? which one is correct configuration? Please provide directions to fill up the tab "BoardDataBusConfig" in the RPA tool.

Thanks

Girish

Re: iMX8M mini DDR Board Data Bus Configuration in RPA tool (MX8M_Mini_LPDDR4_RPA_v15.xlsx)

igorpadykov — Tue, 30 Jun 2020 23:35:27 GMT

Hi Girish

"BoardDataBusConfig" allows for easier board routing since it is possible

to move some data to another processor location. It is described in

sect.9.2.2.3.5.1 Response Data Ordering

i.MX 8M Mini Applications Processor Reference Manual

Also additional file was sent via mail.

Best regards
igor
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Re: iMX8M mini DDR Board Data Bus Configuration in RPA tool (MX8M_Mini_LPDDR4_RPA_v15.xlsx)

girishprasadgm — Wed, 01 Jul 2020 12:43:46 GMT

Hi Igor

Thanks a lot for your reply

As per the Reference manual Register values DWC_DDRPHYA_DBYTEn.DqLnSel

Phy Dq will be mapped to dram dq.

If we swap the lanes A & B ( that is Phy's A lane is connected to DDR's B Lane & Phy's B lane is connected to DDR's A Lane) . In this case which dors RPA tool takes care of this swapping by updating the register values? if not how we need to configure RPA tool tab "BoardDataBusConfig" ?

Thanks

Girish