i.MX ProcessorsのトピックQuestion on i.MX6 LVDS setting

Question on i.MX6 LVDS setting

t_kuha — Wed, 15 Jul 2020 05:54:48 GMT

According to "39.5.1 Mapping of Input Data Busses" in Reference Manual of i.MX6 Quad, when using LVDS channel 1, DI0 in single channel mode is disabled.

The question is: what does this mean?

Does it mean when using LVDS ch1, only IPU*-DI1 can be used (and IPU*-DI0 is not usable)?

Best regards,

Re: Question on i.MX6 LVDS setting

mrudangshelat1 — Wed, 15 Jul 2020 09:42:47 GMT

Hi,

As per Reference Manual section 9.3- LVDS Display Bridge (LDB), LVDS Display Bridge (LDB) will be used to connect the IPU (Image Processing Unit) to the External LVDS Display Interface.

There are 2 LVDS channels. These inputs are used to communicate RGB data and controls to external LCD displays with the LVDS interface or through LVDS receivers. The LVDS ports may be used as follows:
• One single-channel output
• One dual-channel output: single input, split to two output channels
• Two identical outputs: single input sent to both output channels
• Two independent outputs: two inputs sent, each, to a different output channel

Please refer section 39.6.1 LDB Control Register (LDB_CTRL) for register settings.

It means you can use both the channel parallel mode. Let us know for which application or purpose you want to use both.

Mrudang

Re: Question on i.MX6 LVDS setting

t_kuha — Thu, 16 Jul 2020 02:38:05 GMT

Mrudang,

Thank you for the response.

What I want to know is whether DI0 can be used as the input for LVDS CH1 when it is used in "One single-channel output."

(I tried to input RGB data from DI0 to LVDS CH1 without apparent problems, but then what "disabled" in Table 39-5 mean?)

Best regards,

Re: Question on i.MX6 LVDS setting

mrudangshelat1 — Fri, 17 Jul 2020 08:06:18 GMT

Hi,

Yes, it is possible. Please refer to section 39.6.1 LDB Control Register (LDB_CTRL) for register settings.

Table 39-5 provides different use-cases as Single-channel 0/1, Separate channel, Dual Channel, and split channel. And above register settings help you in the above use-cases.

Regards,

Mrudang

Re: Question on i.MX6 LVDS setting

Rita_Wang — Fri, 17 Jul 2020 09:15:14 GMT

Mrudang mentioned the LVDS have the ways use you can see in our RM Table39-5. Recommend you to use following our RM, do not change the order. DI0 to LVDS0 and DI1 to LVDS1.

Re: Question on i.MX6 LVDS setting

t_kuha — Mon, 20 Jul 2020 00:46:59 GMT

Mrudang and Rita,

Thank you for the answer.

I now understand that although it is technically posiible to use IPU* DI0 for LVDS CH1 in single channle output mode,

it is not a recommended use case.

Best regards,

Re: Question on i.MX6 LVDS setting

kiranpatel — Tue, 09 May 2023 10:42:09 GMT

Hi, do you have any recommendations for the 2 channel RGB to LVDS interface ICs? Thanks.