topic Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern? in i.MX Processors

i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Tue, 05 May 2020 13:01:09 GMT

Hi,

I want to use the RGMII interface for connecting a 100Mbps BroadR-Reach PHY. The PHY has its own 25MHz oszillator but no clock output.

Here is my connection between I.MX6 and PHY

i.MX6 BCM89811

RGMII_TXC------------------GTXCLK

RGMII_TX_CTL-------------TX_EN

RGMII_TD0------------------TXD0

RGMII_TD1------------------TXD1

RGMII_TD2------------------TXD2

RGMII_TD3------------------TXD3

RGMII_RXC-----------------RXC

RGMII_RX_CTL------------RX_DV

RGMII_RD0-----------------RXD0

RGMII_RD1-----------------RXD1

RGMII_RD2-----------------RXD2

RGMII_RD3-----------------RXD3

ENET_MDIO---------------MDIO

ENET_MDC----------------MDC

GPIO3_IO7-----------------RESET

The PHY requires a 25MHz clock signal at GTXCLK from the MAC and the i.MX6 requires a 25MHz ENET_REF_CLK signal for the MAC.

Is it possible to generate the 25MHz ENET_REF_CLK internal, send it over the RGMII_TXC pad to the PHY and read it over a level-shifter back to the ENET_REF_CLK?

Or is there a need of a seperate clock signal which feeds the ENET_REF_CLK and the i.MX6 send it through the RGMII_TXC pad to the GTXCLK pin of the PHY?

Thanks

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

Yuri — Wed, 06 May 2020 11:29:48 GMT

Hello,

Use Table 2-9 (Gigabit Ethernet Recommendations), sections 10.4 (Generating the reference clock on chip)

and 10.5 (Using an external clock) of Hardware Development Guide for i.MX6 about recommended ENET clock configurations.

http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf

Table in section 23.6.18 (Ethernet interfaces) of i.MX 6Dual/6Quad Reference Manual, Rev. 5, 06/2018,

shows how to configure ENET registers to select the needed interface (RGMII) and its speed mode.

https://www.nxp.com/webapp/Download?colCode=IMX6DQRM

Regards,

Yuri.

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Wed, 06 May 2020 12:45:01 GMT

Hi Yuri,

thanks for the reply. I suppose it is not possible to generate a 25MHz enet_ref_clk internaly and route it internaly back to pad ENET_REF_CLK (ball V22).

Currently I generate the 25MHz route it to GPIO16 and loop it back externaly to ENET_REF_CLK (V22).

I can talk to the PHY by MDIO and now my connected media converter (BroadR-Reach <-> Ethernet) show a high signal quality. But I can't send a ping.

Every time I send a ping I got a message:

=> ping 192.168.0.75
Using FEC device

ARP Retry count exceeded; starting again
ping failed; host 192.168.0.75 is not alive

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

Yuri — Thu, 07 May 2020 09:26:42 GMT

Hello,

For RGMII a 125 MHz reference clock is required to feed the ENET_REF_CLK input.

Regards,

Yuri.

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Mon, 11 May 2020 11:23:34 GMT

Hello,

but 125MHz reference clock only for 1Gbps, isn't it? My PHY is a 100Mbps, so I need 25MHz.

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

kelleyhicks1973 — Mon, 11 May 2020 11:32:33 GMT

Your article is so useful for us,thanks for sharing. Good stuff!

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Mon, 11 May 2020 12:13:59 GMT

I tried to feed ENET_REF_CLK with 125MHz but then the RGMII_TXC also has 125MHz. The datasheet of my PHY says that it only should be 25MHz. So it seems that the MAC shift the clock from ENET_REF_CLK to RGMII_TXC.

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Mon, 11 May 2020 13:16:53 GMT

Here is my connection between I.MX6 and PHY (100Mbps, PHY can only 100Mbps)

i.MX6 BCM89811

RGMII_TXC----------------->GTXCLK (25MHz)

RGMII_TX_CTL------------>TX_EN

RGMII_TD0----------------->TXD0

RGMII_TD1----------------->TXD1

RGMII_TD2----------------->TXD2

RGMII_TD3----------------->TXD3

RGMII_RXC<----------------RXC (25MHz)

RGMII_RX_CTL<-----------RX_DV

RGMII_RD0<----------------RXD0

RGMII_RD1<----------------RXD1

RGMII_RD2<----------------RXD2

RGMII_RD3<----------------RXD3

ENET_MDIO<------------->MDIO

ENET_MDC--------------->MDC

GPIO3_IO7---------------->RESET

GPIO16 ----------------->ENET_REF_CLK (25MHz)

RGMII Tx side looks fine. I sent a ping in uboot. I investigated the data and they are okay. Data is shifted by rising and falling edge of TXC.

But the RGMII Rx side I don't understand. I sent a ping from host PC to my target. First thing that catch my eye is that it takes the double of time (5760ns instead of 2880ns). It seems that only one edge of RXC is used.

I checked the interface settings of the PHY and it is in RGMII mode.

Any ideas?

Best regards

Michael

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Mon, 11 May 2020 13:42:07 GMT

(Loopback mode in PHY)

(Loopback cable)

When I put the PHY to loopback mode or use a loopback cable the receive timing looks well.????

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

Yuri — Tue, 12 May 2020 07:01:11 GMT

Hello,

Table in section 23.6.18 (Ethernet interfaces) of i.MX 6Dual/6Quad Reference Manual, Rev. 5, 06/2018,shows how to configure ENET registers to select the needed interface (RGMII) and its speed mode.

Are ENET registers correct for Your case?

Regards,

Yuri.

Re: i.MX6 RGMII Interface - ENET_REF_CLK generation intern?

MicMoba — Tue, 12 May 2020 07:04:44 GMT

Hello,

I solved my problem. There are several things.

1. The U-Boot PHY driver returns a wrong speed. So the FEC driver takes 1Gbps.

2. The ENET_REF_CLK has to be 125MHz independent of the PHY's speed

Here is my connection between I.MX6 and PHY (100Mbps, PHY can only 100Mbps)

i.MX6 BCM89811

RGMII_TXC ------------> GTXCLK (25MHz)

RGMII_TX_CTL ------------> TX_EN

RGMII_TD0 ------------> TXD0

RGMII_TD1 ------------> TXD1

RGMII_TD2 ------------> TXD2

RGMII_TD3 ------------> TXD3

RGMII_RXC <------------- RXC (25MHz)

RGMII_RX_CTL<----------- RX_DV

RGMII_RD0 <----------- RXD0

RGMII_RD1 <----------- RXD1

RGMII_RD2 <----------- RXD2

RGMII_RD3 <----------- RXD3

ENET_MDIO <---------> MDIO

ENET_MDC -----------> MDC

GPIO3_IO7 -----------> RESET

GPIO16 -----------> ENET_REF_CLK (125MHz)

I hope it can help somebody who fights with the same problems.