topic About STREAM_FENCING_CONTROL register for i.MX8X in i.MX Processors

About STREAM_FENCING_CONTROL register for i.MX8X

Kazuma_Sasaki — Mon, 18 May 2020 15:06:37 GMT

Hello,

MIPI-CSI2 has STREAM_FENCING_CONTROL register. I have checked following VC enabling patch.

It seems like the STREAM_FENCING_CONTROL register is not using by linux BSP.

Could you please explain me feature of STREAM_FENCING_CONTROL register?

What does "Fence VC0" mean?

ISL79987 and adv7180 de-interlace driver for iMX8QXP boards

From IMX8DQXPRM.pdf (Rev.0)

Best Regards,

Kazuma Sasaki.

Re: About STREAM_FENCING_CONTROL register for i.MX8X

Rita_Wang — Thu, 21 May 2020 08:15:30 GMT

Hi Kazuma Sasaki

The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.

For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.

MIPI CSI2 reset can recover it.

Have a nice day

Best Regards,

Rita

Re: About STREAM_FENCING_CONTROL register for i.MX8X

Kazuma_Sasaki — Mon, 25 May 2020 10:55:11 GMT

Dear Rita Wang,

I appreciate your support. I got it.

Best Regards,

Kazuma Sasaki.