<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: MIPI CSI2 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040252#M153265</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;afaik most detailed info was provided by Tom Zheng on :&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/502102"&gt;Fixing 'base address switching Change Err' which occurs randomly&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 02 Apr 2020 00:41:21 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2020-04-02T00:41:21Z</dc:date>
    <item>
      <title>MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040249#M153262</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a guide similar to the AN5305 (which is for iMX6) for the iMX8MQ?&lt;/P&gt;&lt;P&gt;It would be greatly appreciated,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Simon P. Tsaoussis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Mar 2020 21:32:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040249#M153262</guid>
      <dc:creator>simon6</dc:creator>
      <dc:date>2020-03-31T21:32:20Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040250#M153263</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Simon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately such documentation is not available, sorry.&lt;/P&gt;&lt;P&gt;May be useful to look at linux mipi csi drivers descriptions in&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=L4.19.35_1.1.0_LINUX_DOCS" target="_blank"&gt;Linux 4.19.35_1.1.0 Documentation&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://lore.kernel.org/patchwork/patch/1068551/" title="https://lore.kernel.org/patchwork/patch/1068551/"&gt;[v9,2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs - Patchwork&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Apr 2020 01:17:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040250#M153263</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-04-01T01:17:58Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040251#M153264</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;At the very least is there some information that can help me with the questions asked in:&amp;nbsp;&lt;A href="https://community.nxp.com/thread/484173"&gt;Camera porting guide for MIPI-CSI2 on i.MX8M?&lt;/A&gt;&amp;nbsp; about the clock rates?&amp;nbsp; Because I found this in the iMX8M docs:&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/104368i83882C64B33AB92D/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;But this does not state anything about relationships or limits of the clocks to each other. How do I know my clock configuration is valid?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Apr 2020 15:43:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040251#M153264</guid>
      <dc:creator>simon6</dc:creator>
      <dc:date>2020-04-01T15:43:52Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040252#M153265</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;afaik most detailed info was provided by Tom Zheng on :&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/502102"&gt;Fixing 'base address switching Change Err' which occurs randomly&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Apr 2020 00:41:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI2/m-p/1040252#M153265</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-04-02T00:41:21Z</dc:date>
    </item>
  </channel>
</rss>

