<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: iMX6 POR_B State on Power Up in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035533#M152727</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Mark,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Your system looks good to me.&amp;nbsp;I do not see any start-up issues here&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That particular peak with 3V is maybe because of&amp;nbsp;internal pull-up on POR pin. Even after glitch, the processor&amp;nbsp;will get reset by PMIC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me know if you have any query.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mrudang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 01 Apr 2020 10:41:13 GMT</pubDate>
    <dc:creator>mrudangshelat1</dc:creator>
    <dc:date>2020-04-01T10:41:13Z</dc:date>
    <item>
      <title>iMX6 POR_B State on Power Up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035532#M152726</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We have developed a board using the iMX6 Solo and our own discrete power supplies. The board is running great but we have one final point of concern before running production.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have an external reset generator attached to POR_B which is also wired to another microcontroller so it can also generate a reset to the iMX6.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The reset generator is open-collector and because POR_B is on the SNVS domain has a pull-up to this rail (3.3V).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The reset generator waits for the 1.35V ARM/SOC rail to rise up to 0.9V then waits 200ms before releasing reset. The hardware guide says we have to wait for ARM_CAP, SOC_CAP and&amp;nbsp;PU_CAP to be stable before releasing POR_B. However these are all outputs from the internal LDOs so rather than monitor each we just delay a fixed amount when we know 1.35V has come up enough.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyway - our reset generator is open collector but during power up its output is not asserted until the 1.35V rail rises sufficiently. Because the POR_B pin has a pull-up to 3.3V there is a brief blip on 3.3V for 20ms or so before POR_B is asserted. See below (blue=POR_B, red = 1.35V):&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/96197i2F05834B3CF31709/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The guides say to ensure POR_B is asserted immediately on power up and released once the _CAP rails are up. Will we have any issues with the above waveform on POR_B?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have also seen advice stating that if not using POR_B it can be tied to VDD_SNVS (3.3V) anyway which is what we have briefly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our boards boot every time and reset when this line is asserted. I just want to make sure we won't have startup issues in future!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks, Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Mar 2020 11:43:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035532#M152726</guid>
      <dc:creator>markwilliams</dc:creator>
      <dc:date>2020-03-31T11:43:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 POR_B State on Power Up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035533#M152727</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Mark,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Your system looks good to me.&amp;nbsp;I do not see any start-up issues here&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That particular peak with 3V is maybe because of&amp;nbsp;internal pull-up on POR pin. Even after glitch, the processor&amp;nbsp;will get reset by PMIC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me know if you have any query.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mrudang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Apr 2020 10:41:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035533#M152727</guid>
      <dc:creator>mrudangshelat1</dc:creator>
      <dc:date>2020-04-01T10:41:13Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 POR_B State on Power Up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035534#M152728</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;There is no any issue here. 200ms is enough time for all internal circuits to be properly reset regardless of initial power state.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Apr 2020 09:10:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-POR-B-State-on-Power-Up/m-p/1035534#M152728</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2020-04-06T09:10:44Z</dc:date>
    </item>
  </channel>
</rss>

