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    <title>i.MX ProcessorsのトピックRe: i.MX6UL: RANDOMIZER_ENABLE fuse</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033185#M152513</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please refer to attached i.MX6UL Fusemap spreadsheet that contains the detailed fuses description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 29 Nov 2019 11:07:48 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2019-11-29T11:07:48Z</dc:date>
    <item>
      <title>i.MX6UL: RANDOMIZER_ENABLE fuse</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033184#M152512</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In the i.MX6UL RM, all boot fusemap (QSPI, Serial, ...) are referencing a RANDOMIZER_ENABLE bit at bit 7 of fusemap location 0x6D0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This bit is not described anywhere else in the i.MX6UL RM (or SRM).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Moreover the same location (bit 7 at location 0x6D0) is described at another place in the RM as "Enable boot failure indication pin" without more information (related to fuse location bits 16 .. 19 at location 0x470 ?).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you please provide some clarification on the usage of this particular bit?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;JC&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Nov 2019 09:10:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033184#M152512</guid>
      <dc:creator>jean-christoph4</dc:creator>
      <dc:date>2019-11-25T09:10:19Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL: RANDOMIZER_ENABLE fuse</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033185#M152513</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please refer to attached i.MX6UL Fusemap spreadsheet that contains the detailed fuses description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Nov 2019 11:07:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033185#M152513</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-11-29T11:07:48Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL: RANDOMIZER_ENABLE fuse</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033186#M152514</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Artur,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the fusemap excel spreadsheet. This answers &lt;A _jive_internal="true" href="https://community.nxp.com/thread/518696"&gt;another question&lt;/A&gt; I asked on this forum.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So according to this spreadsheet fuse 7 at 0x6D0 is the "boot failure indicator pin" enabler.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Just out of curiosity, which NXP processor uses a RANDOMIZER_ENABLE bit (at this same location?) and what is it used for in the boot process?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;JC&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Nov 2019 12:32:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-RANDOMIZER-ENABLE-fuse/m-p/1033186#M152514</guid>
      <dc:creator>jean-christoph4</dc:creator>
      <dc:date>2019-11-29T12:32:13Z</dc:date>
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