QSPI Flash cannot be accessed when booted with other than QSPI Boot

yuichi_takeda — Tue, 12 Nov 2019 00:52:24 GMT

Hello, Community.

Previously, when I asked about how to recover from an abnormal image written on the MCIMX7SABRE board, I was advised to boot from an SD card or use a UUU.

Thank you for your suggestion!

I am checking it now.

By the way, I have a question.

I think that QSPI flash can be erased and rewritten if it is set to something other than QSPI Boot so that abnormal programs do not work.

But It couldn't.

When dumping address 0x60000000 at that time, something should be written, but it is filled with all zeros.
I think I can't access QSPI flash for some reason.
Do you know why?

I'm using IAR's Flash loader.

Best regards,

Yuichi Takeda

Re: QSPI Flash cannot be accessed when booted with other than QSPI Boot

igorpadykov — Tue, 12 Nov 2019 05:19:09 GMT

Hi Yuichi

when qspi is used for boot it is properly configured by qspi configuration parameters

described in Table 6-50. QuadSPI configuration parameters i.MX 7Dual Applications Processor Reference Manual

IAR's Flash loader is not supported by nxp, one can try with uboot, check for #ifdef CONFIG_FSL_QSPI in

uboot/include/configs/mx7dsabresd.h

mx7dsabresd.h\configs\include - uboot-imx - i.MX U-Boot

Best regards
igor
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Re: QSPI Flash cannot be accessed when booted with other than QSPI Boot

yuichi_takeda — Tue, 12 Nov 2019 07:48:52 GMT

Hi igor

Thank you for your reply!

The QuadSPI configuration parameters have been written with an abnormal image using the IAR flash loader.
They are as follows.

----------------------

__root const SFLASH_CONFIGURATION_PARAM quadspi_conf = {
0x0, /*dqs_loopback=0 or 1*/
0x0, /*hold_delay=0 to 3*/
0x0, /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0x0, /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
0x0, /*device_quad_mode_en=1 to enable sending command to SPI device*/
0x0, /*device_cmd=command to device for enableing Quad I/O mode*/
0x3000002, /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
0x2000000, /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
0x3, /*cs_hold_time=0 to 0xF*/
0x3, /*cs_setup_time=0 to 0xF*/
0x8000000, /*sflash_A1_size=size in byte(hex)*/
0x0, /*sflash_A2_size=size in byte(hex)*/
0x0, /*sflash_B1_size=size in byte(hex)*/
0x0, /*sflash_B2_size=size in byte(hex)*/
0x0, /*sclk_freq=0 to 6*/
0x0, /*busy_bit_offset=bit position of device BUSY in device status register*/
0x1, /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
0x0, /*sflash_port=0 or 1 (Port B used)*/
0x0, /*ddr_mode_enable=0 or 1*/
0x0, /*dqs_enable=0 or 1*/
0x0, /*parallel_mode_enable=0 or 1*/
0x0, /*portA_cs1=0 or 1*/
0x0, /*portB_cs1=0 or 1*/
0x0, /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0x0, /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
0x0, /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
0x08180403, /*lut[0] command sequence read*/
0x24001c04, /*lut[1] command sequence*/
0x0, /*lut[2] command sequence*/
0x0, /*lut[3] command sequence*/
0x1c020405, /*lut[4] command sequence read status*/
0x2400, /*lut[5] command sequence*/
0x0, /*lut[6] command sequence*/
0x0, /*lut[7] command sequence*/
0x24000406, /*lut[8] command sequence write en*/
0x0, /*lut[9] command sequence*/
0x0, /*lut[10] command sequence*/
0x0, /*lut[11] command sequence*/
0x20010401, /*lut[12] command sequence*/
0x2400, /*lut[13] command sequence*/
0x0, /*lut[14] command sequence*/
0x0, /*lut[15] command sequence*/
0x1c010435, /*lut[16] command sequence*/
0x2400, /*lut[17] command sequence*/
0x0, /*lut[18] command sequence*/
0x0, /*lut[19] command sequence*/
0x0, /*lut[20] command sequence*/
0x0, /*lut[21] command sequence*/
0x0, /*lut[22] command sequence*/
0x0, /*lut[23] command sequence*/
0x0, /*lut[24] command sequence*/
0x0, /*lut[25] command sequence*/
0x0, /*lut[26] command sequence*/
0x0, /*lut[27] command sequence*/
0x0, /*lut[28] command sequence*/
0x0, /*lut[29] command sequence*/
0x0, /*lut[30] command sequence*/
0x0, /*lut[31] command sequence*/
0x0, /*lut[32] command sequence*/
0x0, /*lut[33] command sequence*/
0x0, /*lut[34] command sequence*/
0x0, /*lut[35] command sequence*/
0x0, /*lut[36] command sequence*/
0x0, /*lut[37] command sequence*/
0x0, /*lut[38] command sequence*/
0x0, /*lut[39] command sequence*/
0x0, /*lut[40] command sequence*/
0x0, /*lut[41] command sequence*/
0x0, /*lut[42] command sequence*/
0x0, /*lut[43] command sequence*/
0x0, /*lut[44] command sequence*/
0x0, /*lut[45] command sequence*/
0x0, /*lut[46] command sequence*/
0x0, /*lut[47] command sequence*/
0x0, /*lut[48] command sequence*/
0x0, /*lut[49] command sequence*/
0x0, /*lut[50] command sequence*/
0x0, /*lut[51] command sequence*/
0x0, /*lut[52] command sequence*/
0x0, /*lut[53] command sequence*/
0x0, /*lut[54] command sequence*/
0x0, /*lut[55] command sequence*/
0x0, /*lut[56] command sequence*/
0x0, /*lut[57] command sequence*/
0x0, /*lut[58] command sequence*/
0x0, /*lut[59] command sequence*/
0x0, /*lut[60] command sequence*/
0x0, /*lut[61] command sequence*/
0x0, /*lut[62] command sequence*/
0x0, /*lut[63] command sequence*/
0x1000001, /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/
0x0, /*enable_dqs_phase=0 or 1*/
0x0, /*config_cmds_en, enable config command*/
0x0, /*config_cmds[0]*/
0x0, /*config_cmds[1]*/
0x0, /*config_cmds[2]*/
0x0, /*config_cmds[3]*/
0x0, /*config_cmds_args[0]*/
0x0, /*config_cmds_args[1]*/
0x0, /*config_cmds_args[2]*/
0x0, /*config_cmds_args[3]*/
0x0, /*io_pad_override_setting QSPI pins override setting*/
0x0, /*reserve[0], 25 byte reserved area*/
0x0, /*reserve[1], 25 byte reserved area*/
0x0, /*reserve[2], 25 byte reserved area*/
0x0, /*reserve[3], 25 byte reserved area*/
0x0, /*reserve[4], 25 byte reserved area*/
0x0, /*reserve[5], 25 byte reserved area*/
0x0, /*reserve[6], 25 byte reserved area*/
0x0, /*reserve[7], 25 byte reserved area*/
0x0, /*reserve[8], 25 byte reserved area*/
0x0, /*reserve[9], 25 byte reserved area*/
0x0, /*reserve[10], 25 byte reserved area*/
0x0, /*reserve[11], 25 byte reserved area*/
0x0, /*reserve[12], 25 byte reserved area*/
0x0, /*reserve[13], 25 byte reserved area*/
0x0, /*reserve[14], 25 byte reserved area*/
0x0, /*reserve[15], 25 byte reserved area*/
0x0, /*reserve[16], 25 byte reserved area*/
0x0, /*reserve[17], 25 byte reserved area*/
0x0, /*reserve[18], 25 byte reserved area*/
0x0, /*reserve[19], 25 byte reserved area*/
0x0, /*reserve[20], 25 byte reserved area*/
0x0, /*reserve[21], 25 byte reserved area*/
0x0, /*reserve[22], 25 byte reserved area*/
0x0, /*reserve[23], 25 byte reserved area*/
0x0, /*reserve[24], 25 byte reserved area*/
QSPI_TAG, /*tag, QSPI configuration tag, should be 0xc0ffee01*/
};

----------------------

These should be written at address 0x60000000-, but when booted by other than QSPI Boot, they are all 0 when dumped with IAR EW.

The address 0x60000400-, where the program image should be written, are 0 as well.

When booting with QSPI Boot, the flash loader does not work because of an abnormal program running.
Therefore, I tried to start the flash loader other than QSPI Boot, but I could not access QSPI flash.

Best regards,

Yuichi Takeda

topic QSPI Flash cannot be accessed when booted with other than QSPI Boot in i.MX Processors

QSPI Flash cannot be accessed when booted with other than QSPI Boot

Re: QSPI Flash cannot be accessed when booted with other than QSPI Boot

Re: QSPI Flash cannot be accessed when booted with other than QSPI Boot