i.MX Processors中的主题 Re: DRAM module termination

DRAM module termination

dluberger — Tue, 10 Dec 2019 15:55:47 GMT

It seems my only two options to get 8GB of RAM is either connect 8x 8gb (1GB) DDR3/3L ICs or I was thinking I can just connect to a SODIMM module. If I get a non-ecc module all of the connections seem to make sense and have a direct mapping to the imx ddr physical interface.

The only things not provided directly by this interface are the Serial Presence Detect (SPD)/Temperature/Write Protect I2C interface, which seems to not actually be necessary for RAM operation, though I've connected that I2C bus to I2C0. I'm hoping there's a setting somewhere in the Yocto build that will allow me to specify that I'm using a SODIMM module with SPD so that Linux can make use of the memory timings in EEPROM on the SODIMM module (maybe somewhere in the kernel menuconfig?).

The only other thing that isn't clear to me is how to connect the On-Die Termination (ODT) connections. There are 2 ODT lines on the SODIMM module, and 2 ODT connections on the imx processor, however, in any reference design I look at (e.g., the imx6qpsabresd board) all of the DDR ICs connect to the same ODT line (DRAM_SDODT0) and leave the second ODT line (DRAM_SDODT1) unconnected. Should I do the same here, or connect one to each. I believe on the SODIMM module, ODT0 goes to one group of 4 ICs and ODT1 goes to the second group of 4. Is that because 4 RAM ICs is the limit for parallel connection of the termination line in the imx processor?

The attached screenshots show how I'm connecting the SODIMM module (the file names are just image numbers, not meant to imply there is more than one module; there is only one SODIMM).

Re: DRAM module termination

Yuri — Wed, 11 Dec 2019 09:28:48 GMT

Hello,

Below are some comments regarding the issue:

1) I.MX6 supports up to 3840 MB, according to System memory map in the i.MX6 Reference Manual.

2) If SODIMM SPD should be used, it should be done in U-boot initialization. Use Linux porting Guide

in NXP Linux documentation.
3) ODT0 should be used with CS0, ODT1 - with CS1. For more details:

i.mx6 dual with (2) MT41K256M16 DDR3L

Regards,

Yuri.

Re: DRAM module termination

dluberger — Mon, 16 Dec 2019 18:23:06 GMT

1) This isn't the first time I've made the mistake of not digging through documentation to find the RAM size limit. I really don't understand why this simple but very useful piece of information isn't listed directly on the product page.

2) Can you be more specific? I downloaded the linux documentation package that goes with the kernel I'm using (4.9.88) but I don't see anything in the document IMXBSPPG "i.MX BSP Porting Guide" (the only doc I could find that has "porting guide" in the title) that talks about using SPD or timing info in Uboot from DRAM module EEPROM.

3) Thanks for this info. It's what I needed to know with regards to ODT. Since the module I'm using has two chip select inputs I'm guessing I should connect one ODT pin to ODT 0 and the other to ODT1. Do I then have to set the BOOT_CFG3 lines (pull-ups/-downs at EIM_A23 downto A16) for "DDR Memory fixed 2x32 mapping"? The SODIMM has 64 data lines and 16 address lines, 2 clocks, 2 chip selects, and 3 bank address lines. This appears to be standard for a 204-pin SODIMM regardless of total memory size.

Re: DRAM module termination

Yuri — Tue, 17 Dec 2019 06:29:58 GMT

Hello,

Note, we do not have examples regarding memory with SPD, usually SODIMMs are not used

with i.MX devices. Therefore customers should provide corresponding memory initialization code

themselves from scratch.

As for DDR mapping to MMDC controller ports - use "x64 fixed mapping"

Regards,

Yuri.

Re: DRAM module termination

dluberger — Tue, 17 Dec 2019 17:36:34 GMT

provide corresponding memory initialization code themselves from scratch.

That sounds very complicated. I can't imagine what that would involve. I'm hoping I can just wire this module up, plug it in, and it works without having to do anything in software.

use "x64 fixed mapping"

x64 fixed isn't an option in boot-cfg. Do you mean "00 - Single DDR channel, NOC scheduler enabled, MMDC reorder disabled" for the DDR Memory Map default and extension configs in BOOT_CFG3 settings? This is on page 339 of iMX6DQPRM.

Re: DRAM module termination

Yuri — Wed, 18 Dec 2019 04:46:20 GMT

Hello,

As has been mentioned, i.MX based designs usually do not use DIMMs or SODIMMs,

therefore there are no any "templates" how to use it. Perhaps it would be easier just to

follow reference design scheme.

Regards,

Yuri.