topic Re: i.MX8M memory setup/testing in i.MX Processors

i.MX8M memory setup/testing

pnee — Fri, 27 Mar 2020 14:35:09 GMT

I have a query in relation the MX8M_LPDDR4_RPA_v24.xlsx

https://community.nxp.com/servlet/JiveServlet/download/340179-59-456897/MX8M_LPDDR4_RPA_v24.xlsx

It lists the following DDR PHY addresses.

However the i.MX8M TRM (Rev. 2 08/2019) lists the PHY_DqnSel address as below (i.e DDR_PHY_DQ0LnSel_0 would be 0x3c010140?)

These definitions seem to be at odds with one another. Which one is correct? Or, am I missing something?

Regards,

PJ Nee.

Re: i.MX8M memory setup/testing

gusarambula — Thu, 09 Apr 2020 21:46:57 GMT

Hello PJ Nee,

Please do use the addresses shown on the programming aid spreadsheet. The discrepancy seems to be related to the fact that the documentation for the DDR controller uses 16 bit addresses, as the memory map is part of Synopsys intellectual property.

My apologies for the inconvenience.
Regards,

Re: i.MX8M memory setup/testing

pnee — Tue, 14 Apr 2020 09:03:45 GMT

Ok - but I then have to question all the other PHY addresses in the i.MX8M TRM? Are they also wrong?

As an example take the DWC_DDRPHYA_DBYTE Memory map table below. Are the base addresses and offsets also all wrong?

Re: i.MX8M memory setup/testing

gusarambula — Fri, 01 May 2020 23:15:28 GMT

Hello PJ Nee,

This seems to apply to all DDR PHY values. I inquired internally and the register offset values are already multiplied by 2 in the reference manual in comparison to the DDR PHY documentation. Therefore, if reference manual is used the final address is derived as follows:

address = DDR PHY base address + PHY block address*4 + register offset*2

So for example Dq0lnSel_0:

address = 0x3C00_0000 + 0x1_0000 * 4 + 0x140 * 2 = 0x3C04_0280

I hope this helps!

Regards,