Sequence RAM memory RT1051/RT1052

rubensjunior — Thu, 07 Nov 2019 13:19:11 GMT

Hi friends,

I am development a project (RT1052) where I do not have Flash memory. Then, all my code is in RAM memory (internal RAM + external RAM). However, when I put the external RAM in first position, ocuors the bellow error when is executed.

When I put a internal RAM in first position work fine, but not have enough space for save me code.

Please, I need your help!

CONSOLE MESSAGE:

MCUXpresso IDE RedlinkMulti Driver v10.3 (Feb 7 2019 22:50:02 - crt_emu_cm_redlink build 760)
Found chip XML file in C:/Users/engenharia/Documents/MCUXpressoIDE_10.3.1_2233/workspace_2/MIMXRT1052B_Project_20191106/Debug\MIMXRT1052xxxxB.xml
Reconnected to existing link server
Connecting to probe 1 core 0 (using server started externally) gave 'OK'
Probe Firmware: LPC-LINK2 CMSIS-DAP V5.224 (NXP Semiconductors)
Serial Number: I3FUJ3GU
VID:PID: 1FC9:0090
USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#7&36a63031&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0 after searching for a good core
debug interface type = Cortex-M7 (DAP DP ID 0BD11477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BB9A9 CSt type 0x11 Trace Sink - TPIU
ROM 1 E0043000: CID B105F00D PID 04001BB101 Sys (type 0x0)
NXP: MIMXRT1052xxxxB
DAP stride is 1024 bytes (256 words)
Connected: was_reset=false. was_stopped=false
Awaiting telnet connection to port 3330 ...
GDB nonstop mode enabled
GDB stub (crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.

Re: Sequence RAM memory RT1051/RT1052

jeremyzhou — Fri, 08 Nov 2019 03:24:32 GMT

Hi Rubens Junior

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
You'll basically need to write and then a script that pokes the appropriate registers to set the SDRAM up before your debug session attempts to download the code into the RAM.
I've attached a script, so please follow the figure to add it before debugging the project.

Have a great day,
TIC

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topic Sequence RAM memory RT1051/RT1052 in i.MX Processors

Sequence RAM memory RT1051/RT1052

Re: Sequence RAM memory RT1051/RT1052