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    <title>i.MX ProcessorsのトピックRe: QSPI Flash access for MIMXRT1064</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019599#M150767</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="341778" data-username="1245366615@qq.com" href="https://community.nxp.com/people/1245366615@qq.com"&gt;li shaolong&lt;/A&gt;,&lt;BR /&gt;I reviewed the LUT registration with reference to the QSPI flash data sheet and the attached table.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Wish it helps you!&lt;/SPAN&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Instruction set (continued).png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/106500i61D8EE5C852F062E/image-size/large?v=v2&amp;amp;px=999" role="button" title="Instruction set (continued).png" alt="Instruction set (continued).png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 May 2020 00:41:06 GMT</pubDate>
    <dc:creator>yamakatb</dc:creator>
    <dc:date>2020-05-11T00:41:06Z</dc:date>
    <item>
      <title>QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019591#M150759</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Hello,&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I am using the MIMXRT1064 with QSPI flash on IAR with EWARM IDE.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;Base&amp;nbsp;project&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;SDK_2.7.0_EVK-MIMXRT1064\boards\evkmimxrt1064\component_examples\flash_component\flexspi_nor&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;My QSPI flash manual:&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;A href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.winbond.com%2Fresource-files%2Fw25q256jv%2520spi%2520revg%252008032017.pdf" style="color: #3d9ce7; border: 0px; font-weight: inherit; text-decoration: none; padding: 0px calc(12px + 0.35ex) 0px 0px;" target="_blank"&gt;https://www.winbond.com/resource-files/w25q256jv%20spi%20revg%2008032017.pdf&lt;/A&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I am using the flexspi_nor project from the&amp;nbsp;EWARM as a base project to test code to program and erase the QSPI flash.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;Questions:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;1) If chip erase is applied with the sample settings, values other than 0xFF (mostly 0x22) will be written to the first 1Byte of each page.(ADP and ADS bits of QSPI Flash reads "1".)&lt;BR /&gt;Also, when the page program was performed and the written address was read again, it was found that the written value was lost by 2 bytes.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Is this a problem with the sequence to register in the LUT?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN&gt;2)&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;If so, what settings can be changed to read and write correctly?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Any help is appreciated, thanks.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;T.Y.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;1.After chip erase&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/99156iC49EAC26DC00B5A6/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;2.Write buffer&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/99264iBB2E4299F7EFCC1C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;3.Read&amp;nbsp;buffer&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/99225iC45316897FFEED54/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 14:13:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019591#M150759</guid>
      <dc:creator>yamakatb</dc:creator>
      <dc:date>2020-03-11T14:13:26Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019592#M150760</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;Thank you for your interest in NXP Semiconductor products and&lt;BR /&gt;for the opportunity to serve you.&lt;BR /&gt;It seems a bit weird, it's hard to say that's a problem with the sequence to register in the LUT.&lt;BR /&gt;So whether you can share the actual testing code you run.&lt;BR /&gt;Looking forward to your reply.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Mar 2020 08:34:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019592#M150760</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2020-03-12T08:34:31Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019593#M150761</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jeremyzhou"&gt;jeremyzhou&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Hi ,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for helping me,&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Attached the code.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is it better to create LUT according to QSPI Flash specification like polling_transfer ...?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;T.&amp;nbsp;Y.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Mar 2020 10:56:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019593#M150761</guid>
      <dc:creator>yamakatb</dc:creator>
      <dc:date>2020-03-12T10:56:31Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019594#M150762</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;BR /&gt;Thanks for your reply.&lt;BR /&gt;1) Is it better to create LUT according to QSPI Flash specification like polling_transfer?&lt;BR /&gt;-- After having a brief review of your code, in my opinion, it's a better way to configure the LUT via parsing SFDP table. However, I still suggest you can try to configure the LUT as the flexspi_nor_polling_transfer presents to compare the current method.&lt;BR /&gt;In addition, I suspect the phenomenon may be related to the hardware, you can give a try slow down the flexspiRootClk in flexspi_mem_config_t struct or increase the FlexSPI clock to 130 MHz as the flexspi_nor_polling_transfer does.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Mar 2020 08:31:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019594#M150762</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2020-03-13T08:31:06Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019595#M150763</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jeremyzhou"&gt;jeremyzhou&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;Hi ,&lt;BR /&gt;Thank you for your reply. I am very helpful.&lt;BR /&gt;&amp;gt;-After having a brief review of your code, in my opinion, it's a better way to configure the LUT via parsing SFDP table.However, I still suggest you can try to configure the LUT as the flexspi_nor_polling_transfer presents to compare the current method .&lt;BR /&gt;--Thank you for your feedback. I will refer to it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1) Currently testing based on flexspi_nor_polling_transfer.&lt;BR /&gt;After sending a command during a test, the phenomenon that SEQIDLE is not cleared often occurs. (Sometimes it is cleared.)&lt;BR /&gt;At what timing does this happen?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2)There is still a timing gap at the time of Read / Write.&lt;BR /&gt;What exactly does the phenomenon seem to be related to the hardware?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 11pt;"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 11pt;"&gt;T.&amp;nbsp;Y.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Mar 2020 13:50:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019595#M150763</guid>
      <dc:creator>yamakatb</dc:creator>
      <dc:date>2020-03-13T13:50:23Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019596#M150764</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;BR /&gt;I was wondering if you can share the detailed testing steps and wave signals, it can help me to figure it out.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2020 06:47:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019596#M150764</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2020-03-16T06:47:25Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019597#M150765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jeremyzhou"&gt;jeremyzhou&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank you for your reply.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;1) Currently testing based on flexspi_nor_polling_transfer.&lt;BR /&gt;After sending a command during a test, the phenomenon that SEQIDLE is not cleared often occurs. (Sometimes it is cleared.)&lt;BR /&gt;At what timing does this happen?&lt;BR /&gt;--&amp;gt;The command setting failed, so I corrected it and succeeded.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With the above, we have confirmed the operation based on flexspi_nor_polling_transfer, so we will proceed with this.&lt;/P&gt;&lt;P&gt;Thank you for supporting me.&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 11pt;"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 11pt;"&gt;T.&amp;nbsp;Y.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Mar 2020 04:33:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019597#M150765</guid>
      <dc:creator>yamakatb</dc:creator>
      <dc:date>2020-03-19T04:33:55Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019598#M150766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The&amp;nbsp;command&amp;nbsp;setting&amp;nbsp;failed,&amp;nbsp;so&amp;nbsp;I&amp;nbsp;corrected&amp;nbsp;it&amp;nbsp;and&amp;nbsp;succeeded&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;--&amp;gt;hello&amp;nbsp;T.Y.&amp;nbsp;，I&amp;nbsp;encountered&amp;nbsp;the&amp;nbsp;same&amp;nbsp;problem,&amp;nbsp;could&amp;nbsp;you&amp;nbsp;please&amp;nbsp;show&amp;nbsp;me&amp;nbsp;the&amp;nbsp;detail&amp;nbsp;solution?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 May 2020 07:32:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019598#M150766</guid>
      <dc:creator>1245366615</dc:creator>
      <dc:date>2020-05-09T07:32:09Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019599#M150767</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="341778" data-username="1245366615@qq.com" href="https://community.nxp.com/people/1245366615@qq.com"&gt;li shaolong&lt;/A&gt;,&lt;BR /&gt;I reviewed the LUT registration with reference to the QSPI flash data sheet and the attached table.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Wish it helps you!&lt;/SPAN&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Instruction set (continued).png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/106500i61D8EE5C852F062E/image-size/large?v=v2&amp;amp;px=999" role="button" title="Instruction set (continued).png" alt="Instruction set (continued).png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 May 2020 00:41:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019599#M150767</guid>
      <dc:creator>yamakatb</dc:creator>
      <dc:date>2020-05-11T00:41:06Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI Flash access for MIMXRT1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019600#M150768</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank you for your reply. I am very helpful.And&amp;nbsp;&lt;SPAN style="color: #333333;"&gt;I have solved the problem.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 May 2020 10:34:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-Flash-access-for-MIMXRT1064/m-p/1019600#M150768</guid>
      <dc:creator>1245366615</dc:creator>
      <dc:date>2020-05-11T10:34:10Z</dc:date>
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